Datasheet CY7C131 Equivalent ( PDF )

N.º	Número de pieza	Descripción	Fabricantes	PDF
35	CY7C131	1K x 8 Dual-Port Static RAM CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 1K x 8 Dual-Port Static RAM Features ■ True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1K x 8 organization ■ 0.65 micron CMOS for optimum speed and power ■ High speed access: 15 ns ■ Low opera	Cypress Semiconductor
34	CY7C1310BV18	1.8V Synchronous Pipelined SRAM CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 18-Mbit QDR™-II SRAM 2-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses ■ Double Data Rate (DDR) i	Cypress Semiconductor
33	CY7C1311AV18	(CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture PRELIMINARY CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 18-Mb QDR™-II SRAM 4-Word Burst Architecture Features • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency • Double Dat	Cypress Semiconductor
32	CY7C1311BV18	(CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth • 4-Word Burst for reducing address bus frequency • Double D	Cypress Semiconductor

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Número de pieza	Descripción	Fabricantes	PDF
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