PDF HT82V46 Data sheet ( Hoja de datos )

Número de pieza	HT82V46
Descripción	3-Channel CCD/CIS Analog Signal Processor
Fabricantes	Holtek Semiconductor
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No Preview Available ! HT82V46www.DataSheet.co.kr 16-Bit, 45MSPS, 3-Channel CCD/CIS Analog Signal Processor Features • Operating voltage: 3.3V • Guaranteed won’t miss codes • 9-bit programmable gain • Correlated Double Sampling • 8-bit programmable offset • Programmable clamp voltage • 8-bit wide multiplexed data output format • 8-bit only output mode • 4-bit multiplexed nibble mode • Internal voltage reference • Programmable 4-wire serial interface • Maximum Conversation rate up to 45 MSPS • 28-pin SSOP package Applications • Flatbed document scanners • Film scanners • Digital color copiers • Multifunction peripherals General Description The HT82V46 is a complete analog signal processor for CCD imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of tri-linear color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC and Programmable Gain Amplifier (PGA), and a high performance 16-bit A/ D converter. The CDS amplifiers may be disabled for use with sensors such as Contact Image Sensors (CIS) and CMOS active pixel sensors, which do not require CDS. The 16-bit digital output is available in 8-bit wide multiplexed format. The internal registers are programmed through a 4-wire serial interface, which provides gain, offset and operating mode adjustments. The HT82V46 operates from a single 3.3V power supply, typically consumes 528mW of power. Block Diagram CDS1 CDS2 ADCK REFT REFB CML VINR VING VINB VRLC/VBIAS CLP RLC RLC RLC C1S C2S Timing Control CDS CDS CDS + + + PGA PGA PGA Bandgap Reference + + 3:1 MUX + 16-bit 16 16:8:4 8 ADC MUX Offset Offset Offset DAC DAC DAC RLC 4 DAC 9 8 2 Red Green Blue Red Green Blue PGA REG Offset REG Setup REG1 ~ REG6 Serial Control Interface OEB OD[0:6] OD[7]/SDO SCK SEN SDI AVDD AVSS AVSS DVDD DVDD DVSS Rev. 1.10 1 November 24, 2011 Datasheet pdf - http://www.DataSheet4U.net/ 1 page www.DataSheet.co.kr HT82V46 Symbol Parameter Programmable Gain Amplifier Resolution Gain Equation GMAX GMIN Max Gain, Each Channel Min Gain, Each Channel Channel Matching A/D Converter Resolution Speed Full-scale Input Range 2(VRT - VRB) Supply Currents Total Supply Current Analogue Supply Current Digital Supply Current Power Down Mode Test Conditions Min. Typ. Max. Unit ― ― 9 ― bits ― 0.66 + PGA[8:0] 7.34 / 511 V/V ― ― 7.5 ― V/V ― ― 0.65 ― V/V ― ―1 5% ― ― LOWREF=0 LOWREF=1 ― 16 ― bits ― 45 ― MSPS 2.0 ―― 1.2 V V ― ― 160 ― mA ― ― 130 ― mA ― ― 30 ― mA ― ― 130 ― μA Note: 1. Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC full- scale input range. 2. Input signal limits are the limits within which the full-scale input voltage signal must lie. Timing Specification AVDD=DVDD=3.3V, AVSS=DVSS=0V, TA=25°C, ADCK=45MHz unless otherwise stated. Symbol Parameter Test Conditions Min. Typ. Max. Unit Clock Parameter tADC ADCK Period ― 22 ― ― ns tADH ADCK High Period tADL ADCK Low Period ― 10 11 ― ns ― 10 11 ― ns tC1 CDS1 Pulse High ― 5 ― ― ns tC2 CDS2 Pulse High ― 5 ― ― ns tC1FC2R CDS1 Falling to CDS2 Rising ― 0 ― ― ns tADFC2R tADRC2R ADCK Falling to CDS2 Rising ADCK Rising to CDS2 Rising ― 4 ― ― ns ― 2.5 ― ― ns tADFC2F tC2FADR tADFC1R ADCK Falling to CDS2 Falling CDS2 Falling to ADCK Rising 2 1st ADCK Falling after CDS2 Falling to CDS1 Rising ― 4 ― ― ns ― 1 ― ― ns ― 1 ― ― ns tPR3 3-channel Mode Pixel Rate ― 66 ― ― ns tPR2 2-channel Mode Pixel Rate tPR1 1-channel Mode Pixel Rate ― 44 ― ― ns ― 22 ― ― ns tOD Output Propagation Delay LAT Output Latency. From 1st ADCK Rising Edge after CDS2 Falling to Data Output ― ― ― 8 12 ns ― 7 ― ADCK periods Rev. 1.10 5 November 24, 2011 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page www.DataSheet.co.kr HT82V46 ADCK 16.5 ADCK CDS2 Analog Input (R, G, B) OD[7:0] DLY[1:0] = 00 B R R GGB B R R GGB B R R GGB B R R GGB B RR GGB B RR GGB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB DLY[1:0] = 01 R R GGB B HB LB HB LB HB LB DLY[1:0] = 10 R R GGB B HB LB HB LB HB LB HB : High Byte; LB : Low Byte DLY[1:0] = 11 R R GGB B HB LB HB LB HB LB Figure 6 MODE1 : 3-channel Pixel-by-Pixel ADCK 16.5 ADCK CDS2 Analog Input (R, G, B) OD[7:0] X HB LB X X X X HB LB X X X X HB LB X X X X HB LB X X X X HB LB X X X X HB LB X X X DLY[1:0] = 00 DLY[1:0] = 01 HB LB DLY[1:0] = 10 HB LB DLY[1:0] = 11 HB : High Byte; LB : Low Byte; X : Invalid Data Figure 7 MODE2 : 1-channel Line-by-Line HB LB Rev. 1.10 11 November 24, 2011 Datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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