PDF IS61LF6432A Data sheet ( Hoja de datos )

Número de pieza	IS61LF6432A
Descripción	SYNCHRONOUS FLOW-THROUGH STATIC RAM
Fabricantes	Integrated Silicon Solution
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No Preview Available ! IS61LF6436A IS61LF6432A 64K x 32, 64Kx36 SYNCHRONOUS FLOW-THROUGH STATIC RAM ISSI® www.DataSheet4U.com OCTOBER 2005 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 100-Pin TQFP package • Power Supply: +3.3V VDD +3.3V or 2.5V VDDQ • Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode • Industrial Temperature Available: (-40oC to +85oC) • Lead-free available DESCRIPTION The ISSI IS61LF6432A and IS61LF6436A are high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, memory. IS61LF6432A is organized as 65,536 words by 32 bits. IS61LF6436A is organized as 65,536 words by 36 bits. They are fabricated with ISSI's advanced CMOS technology. The device inte- grates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BWa controls DQa, BWb controls DQb, BWc controls DQc, BWd controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61LF6432A/36A and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order. Linear burst is achieved when this pin is tied LOW. Inter- leave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency 8.5 8.5 11 90 Unit ns ns MHz Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 1 1 page IS61LF6436A IS61LF6432A TRUTH TABLE Operation Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used CE None None None None None External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L X X L L L X X H H X H X X H H X H ISSI® www.DataSheet4U.com CE2 CE2 ADSP ADSC ADV WRITE OE DQ X X X L X X X High-Z X H L X X X X High-Z L X L X X X X High-Z X H H L X X X High-Z L X H L X X X High-Z HL LXXXXQ H L H L X Read X Q H L H L X Write X D X X H H L Read L Q X X H H L Read H High-Z X X X H L Read L Q X X X H L Read H High-Z X X H H L Write X D X X X H L Write X D X X H H H Read L Q X X H H H Read H High-Z X X X H H Read L Q X X X H H Read H High-Z X X H H H Write X D X X X H H Write X D PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW BWE HH HL HL HL LX BWa X H L L X BWb X H H L X BWc X H H L X BWd X H H L X Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 5 5 Page IS61LF6436A IS61LF6432A READ/WRITE CYCLE TIMING ISSI® www.DataSheet4U.com CLK ADSP ADSC ADV Address GW BWE BWd-BWa CE CE2 CE2 OE DATAOUT DATAIN tKC tKH tSS tSH tKL tSS tSH ADSP is blocked by CE inactive tAS tAH RD1 tWS WR1 tWH RD2 RD3 tWS tWH tCES tCEH tWS tWH WR1 CE Masks ADSP tCES tCEH tCES tCEH CE2 and CE2 only sampled with ADSP or ADSC tOEHZ Unselected with CE2 High-Z tKQLZ tKQ High-Z tOEQX 1a tKQ 2a tKQX tKQHZ tDS 1a tDH Single Read Flow-through Single Write tKQ 2b 2c tKQX Burst Read 2d tKQX tKQHZ Unselected Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 11 11 Page

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IS61LF6432A	SYNCHRONOUS FLOW-THROUGH STATIC RAM	Integrated Silicon Solution

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