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PDF HT82K94E Data sheet ( Hoja de datos )
| Número de pieza | HT82K94E | |
| Descripción | USB Multimedia Keyboard Encoder 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT82K94E/HT8w2wKw.D9at4aSAheet4U.com
USB Multimedia Keyboard Encoder 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage:
fSYS=6M/12MHz: 2.2V~5.5V
· 40 bidirectional I/O lines (max.)
· 8-bit programmable timer/event counter with
overflow interrupt (shared with PD4, vector 08H)
· 16-bit programmable timer/event counter and
overflow interrupts (shared with PA7, vector 0CH)
· Crystal oscillator (6MHz or 12MHz)
· Watchdog Timer
· PS2 and USB modes supported
· USB 2.0 low speed function
· 4 endpoints supported (endpoint 0 included)
· 6144´16 program memory ROM
· 224´8 data memory RAM
· One internal USB interrupt (vector 04H)
· All I/O ports support wake-up options
· HALT function and wake-up feature reduce power
consumption
· 8-level subroutine nesting
· Up to 0.33ms instruction cycle with 12MHz system
clock at VDD=5V
· Bit manipulation instruction
· 16-bit table read instruction
· 63 powerful instructions
· All instructions in one or two machine cycles
· Optional 3-battery mode 2.4V LVR/2.6V LVD (±0.1V)
by option, Low battery detector with internal bit
· Optional 2-battery mode 2.2V LVR/2.4V LVD (±0.1V)
by option, Low battery detector with internal bit
· Operating voltage from 4.0V to 5.5V
(For Connect USB/PS2 Mode)
· Operating voltage from 2.2V to 3.3V
(For Pure Cal. Mode)
· 48-pin SSOP package
General Description
This device is an 8-bit high performance RISC architec-
ture microcontroller designed for USB product applica-
tions. It is particularly suitable for use in products such
as keyboards and keyboard with calculator. A HALT fea-
ture is included to reduce power consumption.
The mask version HT82K94A is fully pin and function-
ally compatible with the OTP version HT82K94E device.
The HT82K94A is under development and will be avail-
able soon.
Rev. 1.50
1 October 11, 2007
1 page  
HT82K94E/HwTww8.2DKat9aS4hAeet4U.com
Symbol
Parameter
Test Conditions
VDD Conditions
IOH1
I/O Port Source Current for PA1~PA7,
PB, PC, PD
5V VOH=3.4V
IOH2 I/O Port Source Current for PA0
5V VOH=3.4V
RPH Pull-high Resistance for PA, PB, PC, PD 5V
¾
VLVR Low Voltage Reset
2-battery option
¾
3-battery option
VLVD Low Battery Detecting Voltage
2-battery option
¾
3-battery option
VV33O 3.3V Regulator Output
5V IV33O=-5mA
Min. Typ. Max. Unit
-2 -4 -8
-12 -18 -24
25 50 80
2.1 2.2 2.3
2.3 2.4 2.5
2.3 2.4 2.5
2.5 2.6 2.7
3.0 3.3 3.6
mA
mA
kW
V
V
V
A.C. Characteristics
Symbol
Parameter
Test Conditions
VDD Conditions
Min.
fSYS System Clock (Crystal OSC) 5V ¾
6
fTIMER Timer I/P Frequency (TMR)
5V ¾
0
tWDTOSC Watchdog Oscillator
5V ¾
15
tWDT1 Watchdog Time-out Period (WDT OSC) 5V Without WDT prescaler 4
tWDT2
Watchdog Time-out Period
(System Clock)
¾ Without WDT prescaler ¾
tRES External Reset Low Pulse Width
¾
¾
1
tSST System Start-up Timer Period
Wake-up from HALT
¾ Power-up, Watchdog
Time-out from normal
¾
¾
tINT Interrupt Pulse Width
¾¾
1
Typ.
¾
¾
31
8
1024
¾
1024
1024
¾
Ta=25°C
Max. Unit
12 MHz
12 MHz
70 ms
16 ms
¾ tSYS
¾ ms
¾ tSYS
¾ tWDTOSC
¾ ms
Rev. 1.50
5 October 11, 2007
5 Page 
HT82K94E/HwTww8.2DKat9aS4hAeet4U.com
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMIbit.
Interrupt Source
Priority Vector
USB interrupt
1 04H
Timer/Event Counter 0 overflow 2 08H
Timer/Event Counter 1 overflow 3 0CH
Once the interrupt request flags (TF, USBF) are set,
they will remain in the INTC register until the interrupts
are serviced or cleared by a software instruction. It is
recommended that a program does not use the ²CALL
subroutine² within the interrupt subroutine. Interrupts of-
ten occur in an unpredictable manner or need to be ser-
viced immediately in some applications. If only one stack
is left and enabling the interrupt is not well controlled, the
original control sequence will be damaged once the
²CALL² operates in the interrupt subroutine.
Oscillator Configuration
There is an oscillator circuits in the microcontroller.
O SC1
O SC2
C r y s ta l O s c illa to r
System Oscillator
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. In stead of
a crystal, a resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works within
a period of approximately 31ms. The WDT oscillator can
be disabled by ROM code option to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), or instruction clock (sys-
tem clock divided by 4), determines the ROM code op-
tion. This timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The Watchdog
Timer can be disabled by ROM code option. If the
Watchdog Timer is disabled, all the executions related
to the WDT result in no operation.
Once the internal WDT oscillator (RC oscillator, nor-
mally with a period of 31ms/5V) is selected, it is first di-
vided by 256 (8-stage) to get the nominal time-out
period of 8ms/5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 1s/5V. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. The high nibble and bit 3 of the WDTS are re-
served for user¢s defined flags, which can only be set to
²10000² (WDTS.7~WDTS.3).
S y s te m C lo c k /4
W DT
O SC
ROM
C ode
O p tio n
S e le c t
8 - b it C o u n te r
W D T P r e s c a le r
7 - b it C o u n te r
8 -to -1 M U X
W D T T im e - o u t
Watchdog Timer
W S 0~W S 2
Rev. 1.50
11 October 11, 2007
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT82K94E.PDF ] | |
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