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PDF HT82V42 Data sheet ( Hoja de datos )
| Número de pieza | HT82V42 | |
| Descripción | CIS Analog Signal Processor | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT82V42
CIS Analog Signal Processor
Features
· 3.3V single power supply
· Low power consumption: 188mW (Typ.)
· Power-down mode: 300uA (Typ.)
· 16-bit 15 MSPS A/D converter
· Guaranteed won¢t miss codes
· 8-bit programmable gain
· Correlated Double Sampling
Applications
· Flatbed document scanners
· Film scanners
· ±315mV 8-bit programmable offset
· Programmable clamp voltage
· Internal voltage reference
· Programmable 4-wire serial interface
· 4-bit multiplexed nibble mode
· 20-pin SSOP/TSSOP package
· Digital color copiers
· Multifunction peripherals
General Description
The HT82V42 is a complete analog signal processor for
CCD imaging applications. It features a 1-channel archi-
tecture designed to sample and condition the outputs of
tri-linear color CCD arrays. The channel consists of an
input clamp, Correlated Double Sampler (CDS), offset
DAC and Programmable Gain Amplifier (PGA) and a
high performance 16-bit A/D converter. The CDS ampli-
fiers may be disabled for use with sensors such as Con-
tact Image Sensors (CIS) and CMOS active pixel
sensors, which do not require CDS. The 16-bit digital
output is available in 4-bit wide multiplexed format. The
internal registers are programmed through a 4-wire se-
rial interface, which provides gain, offset and operating
mode adjustments. The HT82V42 operates from a sin-
gle 3.3V power supply and typically consumes 188mW
of power.
Block Diagram
AVDD AVSS VRB VRT VRX
www.DataSheet4U.com
VIN
CDS
RPGA
GPGA
BPGA
3:1
MUX
+ PGA
RDAC
GDAC
BDAC
3:1
MUX
10-Bit
DAC
AVSS
DVDD1
DVDD2 DGND
BANDGAP
Reference
16-Bit
ADC
16
16 : 4
MUX
4
OD[0]
OD[1]
OD[2]
OD[3]/SDO
VRLC/
BAIS
Clamp
DAC
Configuration
Register
RED
GREEN
BLUE
RED
GREEN
BLUE
Offset
Registers
MUX
Register
Gain
Registers
Digital
Control
Interface
SCLK
SEN
SDI
Rev. 1.00
CDSCLK2
DCLK
1
ACYC
November 20, 2009
1 page  
HT82V42
Symbol
Parameter
Test Conditions
VDD Conditions
Digital Supply Current - Active
(DVDD2)
DCLK=30MHz
Supply Current - Full Power
Down Mode
Min.
Typ.
Max.
Unit
¾ 7 ¾ mA
¾ 300 ¾
mA
Note:
1. Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC
full-scale input range.
2. Input signal limits are the limits within which the full-scale input voltage signal must lie.
A.C. Characteristics
AVDD=DVDD1=DVDD2=3.3V, AGND=DGND=0V, Ta=25°C, DCLK=30MHz unless otherwise stated.
Symbol
Parameter
Test Conditions
VDD Conditions
Min. Typ. Max. Unit
Conversion Rate
3.3V
¾
¾ ¾ 15 MSPS
Input Video Timing
AVDD=DVDD1=DVDD2=3.3V, AGND=DGND=0V, Ta=25°C, DCLK=30MHz unless otherwise stated.
Symbol
Parameter
Min.
Typ.
Max.
tPER DCLK period
33.3
¾
¾
www.DataSheet4Ut.DcCoLmKH
tDCLKL
DCLK high period
DCLK low period
16.6
16.6
¾
¾
¾
¾
tVSMPSU CDSCLK2 setup time
6 ¾¾
tVSMPH CDSCLK2 hold time
3 ¾¾
tVSU Video level setup time
10 ¾ ¾
tVH Video level hold time
3 ¾¾
tRSU Reset level setup time
10 ¾ ¾
tRH Reset level setup time
3 ¾¾
Note : 1. tVSU and tRSU denote the setup time require after the input video signal has settled.
2. Parameters are measured at 50% of the rising/falling edge.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 1.00
5 November 20, 2009
5 Page 
HT82V42
Input Sampling Block: Input Sampling and Referencing
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the input video.
V1 = VIN - VRESET...................................................................Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead.
V1 = VIN - VVRLC .....................................................................Eqn. 2
If VRLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.
If VRLCEXT = 0, VVRLC is the output from the internal RLC DAC.
VVRLC = (VRLCSTEP ´ RLCV[3:0]) + VRLCBOT....................Eqn. 3
VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.
OFFSET DAC Block: OFFSET (BLACK - LEVEL) Adjust
The resultant signal V1 is added to the Offset DAC output.
V2 = V1 + { 315mV ´ (DAC[7:0] - 127.5) } / 127.5.....................Eqn. 4
PGA NODE: GAIN Adjust
The signal is then multiplied by the PGA gain,
V3 = V2 ´ [186 / (278 - PGA[7:0] ) ]...........................................Eqn. 5
ADC Block: Analogue-Digital Conversion
The analogue signal is then converted to a 16-bit unsigned number, with input range configured by PGAFS[1:0].
D1[15:0] = INT{ (V3 /VFS) ´ 65535} + 32767 PGAFS[1:0] = 00 or 01 .................Eqn. 6
D1[15:0] = INT{ (V3 /VFS) ´ 65535}
PGAFS[1:0] = 11 ..........................Eqn. 7
D1[15:0] = INT{ (V3 /VFS) ´ 65535} + 65535 PGAFS[1:0] = 10 ..........................Eqn. 8
where the ADC full-scale range, VFS = 2.0V
if D1[15:0] < 0
D1[15:0] = 0
if D1[15:0] > 65535 D1[15:0] = 65535
Output Invert Block: Polarity Adjust
The polarity of the digital output may be inverted by control bit INVOP.
D2[15:0] = D1[15:0]
www.DataSheet4U.com D2[15:0] = 65535 - D1[15:0]
(INVOP = 0).....................................................Eqn. 9
(INVOP = 1)...................................................Eqn. 10
Output Formats
Latency of valid output data with respect to CDSCLK2 is
programmable by writing to control bits DEL[1:0]. The
latency for each mode is shown in the Operating Mode
Timing Diagrams section. Figure shows the output data
formats for Modes 1, 3 and 4. Figure shows the output
data formats for Mode 2. Table summarizes the output
data obtained for each format.
M C LK
4 + 4 + 4 + 4 - B it
O u tp u t
ABCD
Output Data Formats (Mode 1, 3, 4)
M C LK
4 + 4 + 4 + 4 - B it
O u tp u t
ABABCD
Output Data Formats (Mode 2)
Output Format Output Pins
Output
4+4+4+4-Bit
(Nibble)
OD3~OD0
A= d15~d12
B= d11~d8
C= d7~d4
D= d3~d0
Details of Output Data
Rev. 1.00
11 November 20, 2009
11 Page | ||
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| PDF Descargar | [ Datasheet HT82V42.PDF ] | |
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