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PDF HT82D22R Data sheet ( Hoja de datos )
| Número de pieza | HT82D22R | |
| Descripción | 27MHz Two Channel RX 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT82D22R/HT82D22A
27MHz Two Channel RX 8-Bit MCU
Features
· USB Specification Compliance
- Conforms to USB specification V2.0
- Conforms to USB HID specification V1.11
· Supports 1 Low-speed USB control endpoint and
2 interrupt endpoint
· Single 8-bit programmable timer counter with
overflow interrupt
· Single 16-bit programmable timer counter with
overflow interrupt
· PS2 and USB modes supported
· Built-in two 27MHz FSK Receiver
· Supply 27MHz FSK Receiver power down function
· 8-level stacks
· Each endpoint has 8 bytes FIFO
· Integrated USB transceiver
· 3.3V regulator output
· Integrated 27MHz FSK Receiver
· 27MHz FSK Receiver power down function
· FSK Receiver Frequency range 26.995~27.295MHz
· FSK Receiver High sensitivity: £ -90 dBm
· RF tuner, mixer, transistors, passives, coils, and
SAW filter functions integrated in the same device
· Integrated FSK Receiver Phase Locked Loop
· Eight user selectable frequencies
· Integrated FSK Receiver 6Kbps data rate
· External 12MHz crystal
· 8-bit RISC microcontroller, with 4K´15 EPROM
(000H~FFFH)
· 160 bytes RAM (20H~BFH)
· 6MHz internal MCU clock
· Two 8-bit indirect addressing registers
· Single USB interrupt input (vector 04H)
· HALT function and wake-up feature reduce
power consumption
· All I/O ports support wake-up function
· Internal Power-On reset (POR)
· Watchdog Timer (WDT)
· 10 I/O ports
· 48-pin QFN package
General Description
USB Encoder Built-in two 27MHz FSK Receiver MCU
OTP body is suitable for USB interface and 27MHz
Wireless system. Flexible total solution for applications
that combine PS/2 and low-speed USB interface and
27MHz wireless system, such as mice, joysticks, and
many others
It consists of a Holtek high performance 8-bit MCU core
for control unit, built-in USB SIE, 27MHz FSK Receiver ,
4K´15 ROM and 160 bytes data RAM
www.DataSheet4U.com
Rev. 1.00
1 November 6, 2009
1 page  
HT82D22R/HT82D22A
Symbol
Parameter
VDD
RPH1 Pull-high Resistance for DATA* ¾
RPH2
Pull-high Resistance for PA, PB,
PC, PD
¾
RPH3
Pull-high Resistance for PA, PB0,
PC0
5V
VLVR Low Voltage Reset
5V
Test Conditions
Conditions
¾
¾
¾
¾
Note: ²*² The DATA pull-high must be implemented by the external 1.5kW.
²**² include 15kW loading of USBD+, USBD- line in host terminal.
A.C. Characteristics
Symbol
Parameter
Test Conditions
VDD Conditions
fSYS System Clock (Crystal OSC)
5V
¾
fXTAL Quartz xtal Frequency
¾
¾
Xppm Quartz xtal Frequency Tolerance ¾
¾
CXTAL Xtal Shunt Capacitance
¾
¾
tWDT
Watchdog Time-out Period
(System Clock)
¾ Without WDT prescaler
tRES External Reset Low Pulse Width ¾
¾
Wake-up from HALT
tSST System Start-up Timer Period ¾ Power-up, Watchdog
Time-out from normal
tOSC
Crystal Setup
¾¾
tDEV
27MHz therefore Signal Input
Frequency Deviation
5V
¾
tWDTOSC Watchdog Oscillator
5V ¾
www.DataSheet4U.com
Min. Typ. Max. Unit
1.3 1.5 2.0 kW
2.0 4.7 6.0 kW
25 50 80 kW
2.4 2.7
3
V
Ta=25°C
Min. Typ. Max. Unit
¾
¾
¾
¾
1024
1
¾
3.2
15
6
12
±50
47
¾
¾
1024
1024
5
¾
31
¾ MHz
¾ MHz
¾ ppm
¾ pF
¾ tRCSYS
¾ ms
¾ tSYS
tWDTOSC
10 ms
¾ kHz
70 us
Rev. 1.00
5 November 6, 2009
5 Page 
HT82D22R/HT82D22A
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, opera-
tions related to the status register may give different re-
sults from those intended.
The TO flag can be affected only by a system power-up,
a WDT time-out or executing the ²CLR WDT² or ²HALT²
instruction. The PDF flag can be affected only by exe-
cuting the ²HALT² or ²CLR WDT² instruction or during a
system power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, upon entering the interrupt sequence or exe-
cuting a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
to set the enable/disable and the interrupt request flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the inter-
rupt request will not be acknowledged, even if the re-
lated interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be pre-
vented from becoming full.
All these kinds of interrupts have a wake-up capability.
www.DataSheet4UA.scoamn interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at a specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register (STATUS) are altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
The USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC) will be set.
· Access of the corresponding USB FIFO from PC
· The USB suspend signal from PC
· The USB resume signal from PC
· USB Reset signal
When the interrupt is enabled, the stack is not full and
the external interrupt is active, a subroutine call to loca-
tion 04H will occur. The interrupt request flag (USBF)
and EMI bits will be cleared to disable other interrupts.
When the PC Host access the FIFO, the corresponding
request bit of the USR is set, and a USB interrupt is trig-
gered. So user can easily decide which FIFO is ac-
cessed. When the interrupt has been served, the
corresponding bit should be cleared by firmware. When
the device receives a USB Suspend signal from the
Host PC, the suspend line (bit0 of the USC) is set and a
USB interrupt is also triggered.
When the device receives a Resume signal from the
Host PC, the resume line (bit3 of the USC) are set and a
USB interrupt is triggered.
Whenever a USB reset signal is detected, the USB in-
terrupt is triggered and URST bit of the USC register is
set. When the interrupt has been served, the bit should
be cleared by firmware.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 5 of INTC), caused by a timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further in-
terrupts.
The internal Timer/Even Counter 1 interrupt is initialized
Bit No.
0
1
2
3
4
5
6
7
Label
EMI
EUI
ET0I
ET1I
USBF
T0F
T1F
Function
Controls the master (global) interrupt (1=enable; 0=disable)
Controls the USB interrupt (1=enable; 0= disable)
Controls the Timer/Event Counter0 interrupt (1=enable; 0=disable)
Controls the Timer/Event Counter1 interrupt (1=enable; 0=disable)
USB interrupt request flag (1=active; 0=inactive)
Internal Timer/Event counter0 request flag (1:active; 0:inactive)
Internal timer/event counter request flag (1:active; 0:inactive)
¾ Unused bit, read as ²0²
INTC (0BH) Register
Rev. 1.00
11 November 6, 2009
11 Page | ||
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| PDF Descargar | [ Datasheet HT82D22R.PDF ] | |
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