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XR16M781 の電気的特性と機能

XR16M781のメーカーはExar Corporationです、この部品の機能は「1.62V TO 3.63V UART」です。


製品の詳細 ( Datasheet PDF )

部品番号 XR16M781
部品説明 1.62V TO 3.63V UART
メーカ Exar Corporation
ロゴ Exar Corporation ロゴ 




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XR16M781 Datasheet, XR16M781 PDF,ピン配置, 機能
XR16M781
1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE
AUGUST 2009
REV. 1.0.1
GENERAL DESCRIPTION
The XR16M7811 (M781) is an enhanced Universal
Asynchronous Receiver and Transmitter (UART) with
a VLIO bus interface and has 64 bytes of transmit
and receive FIFOs, programmable transmit and
receive FIFO trigger levels, automatic hardware and
software flow control, and data rates of up to 20 Mbps
at 3.3V, 16 Mbps at 2.5V and 10 Mbps at 1.8V with
4X data sampling rate.
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection
increases the performance by simplifying the
software routines.
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. Power consumption of the
M781 can be minmized by enabling the sleep mode
and PowerSave mode.
The M781 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M781 is available in 24-pin
QFN, 32-pin QFN and 25-pin BGA packages.
NOTE: 1 Covered by U.S. Patent #5,649,122.
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FEATURES
VLIO bus interface
Pin-to-pin compatible with SC16C850V and
SC16C850SV in 32-QFN package
20 Mbps maximum data rate
Programmable TX/RX FIFO Trigger Levels
TX/RX FIFO Level Counters
Independent TX/RX Baud Rate Generator
Fractional Baud Rate Generator
Auto RTS/CTS Hardware Flow Control
Auto XON/XOFF Software Flow Control
Auto RS-485 Half-Duplex Direction Control
Multidrop mode w/ Auto Address Detect
Sleep Mode with Automatic Wake-up
PowerSave mode
Infrared (IrDA 1.0 and 1.1) mode
1.62V to 3.63V supply operation
Crystal oscillator or external clock input
APPLICATIONS
Personal Digital Assistants (PDA)
Cellular Phones/Data Devices
Battery-Operated Devices
Global Positioning System (GPS)
Bluetooth
FIGURE 1. XR16M781 BLOCK DIAGRAM
PwrSave
LLA#
AD7:AD0
IOR#
IO W #
CS#
INT
RESET#
VLIO Bus
Interface
TX
BRG 64 Byte TX FIFO
UART
IR TX &
Regs ENDEC RX
RX
BRG
64 Byte RX FIFO
Crystal Osc/Buffer
VCC
(1.62 to 3.63 V)
GND
TX, RX,
RTS#, CTS#,
DTR#, DSR#,
RI#, CD#
XTAL1
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

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XR16M781 pdf, ピン配列
REV. 1.0.1
PIN DESCRIPTIONS
XR16M781
1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE
Pin Description
NAME
24-QFN
PIN#
32-QFN
PIN#
25-BGA
PIN#
TYPE
DESCRIPTION
DATA BUS INTERFACE
AD0 20 29 C1 I/O Multiplexed Address/Data lines [7:0]. The register address is
AD1 21 30 D2
latched on the rising edge of the LLA#. After the LLA# signal goes
AD2 22 31 E2
AD3 23 32 D1
high, the UART enters the data phase where the data is placed on
these lines.
AD4 24 1 E1
AD5 1 3 B2
AD6 2 4 E3
AD7 3 5 C2
IOR# 12 14 A5 I Read strobe (active low). The falling edge instigates an internal
read cycle and retrieves the data byte from an internal register
pointed by the latched address. The UART places the data byte on
the data bus to allow the host processor to read it on the rising
edge.
IOW# 10 12 E5 I Write strobe (active low). The falling edge instigates the internal
write cycle and the rising edge transfers the data byte on the data
bus to an internal register pointed by the latched address.
CS# 6 8 D3 I Chip select (active low). The falling edge starts the access to the
UART. A read or write is determined by the IOR# and IOW# sig-
nals.
LLA# 14 19 A4 I Latch Lower Address (active low). The register address is latched
on the rising edge of the LLA# signal. After the LLA# goes high, the
device enters the data phase where the data is placed on the
AD[7:0] lines.
INT 15 20 B4 O Interrupt output (active high). The output state is defined by the
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user through the software setting of MCR[3]. INT is set to the active
mode when MCR[3] is set to a logic 1. INT is set to the three state
mode when MCR[3] is set to a logic 0. See MCR[3].
MODEM OR SERIAL I/O INTERFACE
TX 5 7 E4
RX 4 6 C3
RTS# 16 21 A3
O UART Transmit Data or infrared encoder data. Standard transmit
and receive interface is enabled when MCR[6] = 0. In this mode,
the TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
I UART Receive Data or infrared receive data. Normal receive data
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
O UART Request-to-Send (active low) or general purpose output.
This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1] and IER[6]. This pin can also be used as the
Auto RS-485 Half-duplex Direction control output, see FCTR[3] and
EMSR[3].
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XR16M781 電子部品, 半導体
XR16M781
1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE
REV. 1.0.1
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is a VLIO bus interface. The VLIO bus interface is an 8-bit multiplexed address/data bus
interface. Each bus cycle is asynchronous using CS#, LLA# and IOR# or IOW# inputs. A typical data bus
interconnection for the VLIO bus interface is shown in Figure 3.
FIGURE 3. XR16M781 TYPICAL VLIO DATA BUS INTERCONNECTIONS
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
UART_IOR#
UART_IOW#
UART_CS#
UART_INT
POWERSAVE
UART_RESET#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
IOR#
IOW#
CS#
INT
PWRSAVE
RESET#
VCC
VCC
TX
RX
DTR#
RTS#
CTS#
DSR#
CD#
RI#
GND
Serial Transceivers of
RS-232
RS-485
RS-422
Or Infrared
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共有リンク

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部品番号部品説明メーカ
XR16M780

1.62V TO 3.63V HIGH PERFORMANCE UART

Exar Corporation
Exar Corporation
XR16M781

1.62V TO 3.63V UART

Exar Corporation
Exar Corporation


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