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WV3HG2128M72AER-D6 の電気的特性と機能

WV3HG2128M72AER-D6のメーカーはWhite Electronic Designsです、この部品の機能は「2GB - 2x128Mx72 DDR2 SDRAM REGISTERED」です。


製品の詳細 ( Datasheet PDF )

部品番号 WV3HG2128M72AER-D6
部品説明 2GB - 2x128Mx72 DDR2 SDRAM REGISTERED
メーカ White Electronic Designs
ロゴ White Electronic Designs ロゴ 




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WV3HG2128M72AER-D6 Datasheet, WV3HG2128M72AER-D6 PDF,ピン配置, 機能
White Electronic Designs WV3HG2128M72AER-D6
ADVANCED*
2GB – 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL
FEATURES
240-pin, dual in-line memory module
Fast data transfer rates: PC2-4200 and PC2-3200
Utilizes 533 and 400 Mb/s DDR2 SDRAM
components
VCC = VCCQ = 1.8V± 0.1V
VCCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3 and 4
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
Product is lead-free
wwwR.DoaHtaSShceoemt4pUli.acnomt
Dual Rank
Package option
• 240 Pin DIMM
• PCB – 29.97mm (1.18")
DESCRIPTION
The WV3HG2128M72AER is a 128Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of thirty six 128Mx4 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
Clock Speed
CL-tRCD-tRP
PC2-3200
200MHz
3-3-3
PC2-4200
266MHz
4-4-4
September
2005 Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 Page





WV3HG2128M72AER-D6 pdf, ピン配列
White Electronic Designs WV3HG2128M72AER-D6
ADVANCED*
FUNCTIONAL BLOCK DIAGRAM
VSS
RCS1#
RCS0#
DQS0
DQS0#
DQD
DQ1
DQ2
DQ3
DQS1
DQS1#
DQ8
DQ9
DQ10
DQ11
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS2
DQS2#
DQ16
DQ17
DQ18
DQ19
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS3
DQS3#
DQ24
DQ25
DQ26
DQ27
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS4
DQS4#
DQ32
DQ33
DQ34
DQ35
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS5
DQS5#
DQ40
DQ41
DQ42
DQ43
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS6
DQS6#
DQ48
DQ49
DQ50
DQ51
DM
I/O 0
I/O 1
I/O 2
I/O 3
www.DataSheeDDQtQ4SS7U#7 .com
DQ56
DQ57
DQ58
DQ59
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS8
DQS8#
CB0
CB1
CB2
CB3
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DQS9
DQS9#
DQ4
DQ5
DQ6
DQ7
DQS10
DQS10#
DQ12
DQ13
DQ14
DQ15
DQS11
DQS11#
DQ20
DQ21
DQ22
DQ23
DQS12
DQS12#
DQ28
DQ29
DQ30
DQ31
DQS13
DQS13#
DQ36
DQ37
DQ38
DQ39
DQS14
DQS14#
DQ44
DQ45
DQ46
DQ47
DQS15
DQ15#
DQ52
DQ53
DQ54
DQ55
DQS16
DQ16#
DQ60
DQ61
DQ62
DQ63
DQS17
DQ17#
CB4
CB5
CB6
CB7
DM CS# DQS DQS# DM CS# DQS DQS#
I/O 0 I/O 0
I/O 1 I/O 1
I/O 2 I/O 2
I/O 3 I/O 3
DM CS# DQS DQS# DM CS# DQS DQS#
I/O 0 I/O 0
I/O 1 I/O 1
I/O 2 I/O 2
I/O 3 I/O 3
DM CS# DQS DQS# DM CS# DQS DQS#
I/O 0 I/O 0
I/O 1 I/O 1
I/O 2 I/O 2
I/O 3 I/O 3
DM CS# DQS DQS# DM CS# DQS DQS#
I/O 0 I/O 0
I/O 1 I/O 1
I/O 2 I/O 2
I/O 3 I/O 3
DM CS# DQS DQS# DM CS# DQS DQS#
I/O 0 I/O 0
I/O 1 I/O 1
I/O 2 I/O 2
I/O 3 I/O 3
DM CS# DQS DQS# DM CS# DQS DQS#
I/O 0 I/O 0
I/O 1 I/O 1
I/O 2 I/O 2
I/O 3 I/O 3
DM CS# DQS DQS# DM CS# DQS DQS#
I/O 0 I/O 0
I/O 1 I/O 1
I/O 2 I/O 2
I/O 3 I/O 3
DM CS# DQS DQS# DM CS# DQS DQS#
I/O 0 I/O 0
I/O 1 I/O 1
I/O 2 I/O 2
I/O 3 I/O 3
DM CS# DQS DQS# DM CS# DQS DQS#
I/O 0 I/O 0
I/O 1 I/O 1
I/O 2 I/O 2
I/O 3 I/O 3
CS0#
CS1#
BA0 - BA1
A0 - A13
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
RESET#
PCK7
PCK7#
1:4
R
E
G
I
S
T
E
R
RST#
RCS0# CS#: DDR2 SDRAMs
RCS1# CS#: DDR2 SDRAMs
RBA0-RBA1# BA0-BA1 : DDR2 SDRAMs
RA0-RA13 A0-A13 : DDR2 SDRAMs
RRAS# RAS# : DDR2 SDRAMs
RCAS# CAS#: DDR2 SDRAMs
RWE# WE#: DDR2 SDRAMs
RCKE0 CKE : DDR2 SDRAMs
RCKE1 CKE : DDR2 SDRAMs
RODT0 DDR2 SDRAMs
RODT1 DDR2 SDRAMs
NOTE: All resistor values are 22 ohms unless otherwise specified.
Serial PD
SCL
WP A0 A1 A2
SA0 SA1 SA2
SDA
VCCSPD
VCC/VCCQ
VREF
VSS
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
CK0
CK0#
RESET#
P
L
L
OE
PCK0-PCK6, PCK8, PCK9 CK : DDR2 SDRAMs
PCK0#-PCK6#, PCK8#, PCK9#
PCK7 CK : Register
PCK7# CK# : Register
CK# : DDR2 SDRAMs
September
2005 Rev. 0
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com


3Pages


WV3HG2128M72AER-D6 電子部品, 半導体
White Electronic Designs WV3HG2128M72AER-D6
ADVANCED*
DDR2 IDD SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Symbol Proposed Conditions
534 403 Units
IDD0* Operating one bank active-precharge current;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
2284 2284
mA
IDD1* Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD);
CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus input
are switching; Data pattern is same as IDD6W
2554
2554
mA
IDD2P**
Precharge power-down current;
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
988 988 mA
IDD2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
1780
1780
mA
IDD2N**
Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
1960 1960
mA
IDD3P**
Active power-down current;
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0mA
Slow PDN Exit MRS(12) = 1mA
1780
1132
1780
1132
mA
mA
IDD3N**
Active standby current;
All banks open; tCK = tCK(IDD), tRC = tRC(IDD); tRAS = tRASmax(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
www.DataSbhuseientp4uUts.acroemSWITCHING
IDD4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W
IDD5** Burst auto refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD6** Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Normal
IDD7* Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =
tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are STABLE during DESELECTs; Data bus imputs are switching.
Notes:
IDD specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
* Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P ( CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
2500
2824
2914
5740
288
4804
2500
2644
2734
5740
288
4804
mA
mA
mA
mA
mA
mA
September
2005 Rev. 0
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page



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部品番号部品説明メーカ
WV3HG2128M72AER-D6

2GB - 2x128Mx72 DDR2 SDRAM REGISTERED

White Electronic Designs
White Electronic Designs


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