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WV3HG128M72EEU-PD4 の電気的特性と機能

WV3HG128M72EEU-PD4のメーカーはWhite Electronic Designsです、この部品の機能は「1GB - 128Mx72 DDR2 SDRAM UNBUFFERED」です。


製品の詳細 ( Datasheet PDF )

部品番号 WV3HG128M72EEU-PD4
部品説明 1GB - 128Mx72 DDR2 SDRAM UNBUFFERED
メーカ White Electronic Designs
ロゴ White Electronic Designs ロゴ 




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WV3HG128M72EEU-PD4 Datasheet, WV3HG128M72EEU-PD4 PDF,ピン配置, 機能
White Electronic Designs WV3HG128M72EEU-PD4
ADVANCED*
1GB – 128Mx72 DDR2 SDRAM UNBUFFERED, SO-DIMM w/PLL
FEATURES
Unbuffered 200-pin (SO-DIMM) small-outline dual
in-line memory module
Support ECC detection and correction
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
VCC = VCCQ = 1.8V ±0.1V
VCCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Differential clock input (CK,CK#)
Four-bit prefetch architecture
Multiple internal device banks for concurrent
operation
Programmable CAS# latency (CL): 3 4, 5*, and 6*
Adjustable data-output drive strength
7.8µs average periodic refresh interval
On-die termination (ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms: 8,192 cycle refresh)
wwwG.DoaltdaSehdegeet4cUo.ncotamcts
RoHS compliant
JEDEC proposed pin-out
Package option
• 200 Pin SO-DIMM: 30.00mm (1.181") TYP
DESCRIPTION
The WV3HG128M72EEU is a 128Mx72 Double Data Rate
DDR2 SDRAM high density module. This memory module
consists of nine 128Mx8 bit DDR2 Synchronous DRAMs
in FBGA packages, mounted on a 200-pin SO-DIMM FR4
substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
May 2006
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 Page





WV3HG128M72EEU-PD4 pdf, ピン配列
White Electronic Designs WV3HG128M72EEU-PD4
ADVANCED
CS0#
DQS0
DQS0#
DM0
DQS1
DQS1#
DM1
DQS2
DQS2#
DM2
DQS3
DQS3#
DM3
www.DataSheet4U.com
DQS8
DQS8#
DM8
CS0#
BA0-BA2
A0-A13
RAS#
CAS#
WE#
CKE0
ODT0
FUNCTIONAL BLOCK DIAGRAM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM/ CS# DQS DQS#
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/ CS# DQS DQS#
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM/ CS# DQS DQS#
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM/ CS# DQS DQS#
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
DQS4#
DM4
DQS5
DQS5#
DM5
DQS6
DQS6#
DM6
DQS7
DQS7#
DM7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM/ CS# DQS DQS#
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM/ CS# DQS DQS#
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM/ CS# DQS DQS#
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM/ CS# DQS DQS#
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/ CS# DQS DQS#
VCCSPD
RDQS
CB0 I/O 0
VCC\VCCQ
CB1 I/O 1
CB2
CB3
CB4
I/O 2
I/O 3
I/O 4
SCL Serial PD
WP A0 A1 A2
SDA
VREF
VSS
CB5 I/O 5
SA0 SA1 SA2
CB6 I/O 6
CB7 I/O 7
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
CS0# CS#: DDR2 SDRAMs
BA0-RBA2 BA0-BA2: DDR2 SDRAMs
A0-RA13 A0-A13: DDR2 SDRAMs
RAS# RAS#: DDR2 SDRAMs
CAS# CAS#: DDR2 SDRAMs
WE# WE#: DDR2 SDRAMs
CKE0 CKE: DDR2 SDRAMs
ODT0 ODT: DDR2 SDRAMs
CK0
CK0#
P
L
L
PCK0, PCK4-PCK6, PCK9 CK: DDR2 SDRAMs
PCK0# , PCK4#-PCK6#, PCK9# CK#: DDR2 SDRAMs
NOTE: Unless otherwise noted, resistor values are 22 Ohms ± 5%
May 2006
Rev. 0
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com


3Pages


WV3HG128M72EEU-PD4 電子部品, 半導体
White Electronic Designs WV3HG128M72EEU-PD4
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
VCC = +1.8V ± 0.1V
Symbol Proposed Conditions
806 665 534 403 Units
ICC0* Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD 1,110 1,065 1,020 mA
ICC1*
ICC2P*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
TBD 1,200 1,115 1,1110 mA
TBD 408 408 408 mA
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
TBD 660 615 615 mA
ICC2N**
ICC3P**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
Fast PDN Exit MRS(12) = 0
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING Slow PDN Exit MRS(12) = 1
TBD 705 660 660 mA
TBD 570 525 525 mA
TBD 408 408 408 mA
ICC3N** Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
TBD
750
705
705
mA
SWITCHING
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
www.DatatRSAhSmeaext(4ICUC.)c, toRmP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
TBD 1,645 1,470 1,362 mA
ICC4R* Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
TBD
1,645 1,470 1,335
mA
inputs are SWITCHING; Data pattern is same as ICC4W
ICC5B**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
TBD 2,280 2,235 2,190 mA
ICC6** Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs
are FLOATING; Data bus inputs are FLOATING
Normal
TBD 90 90 90 mA
ICC7* Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK =
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
TBD 3,000 2,820 2,640 mA
ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Note:
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
May 2006
Rev. 0
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page



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部品番号部品説明メーカ
WV3HG128M72EEU-PD4

1GB - 128Mx72 DDR2 SDRAM UNBUFFERED

White Electronic Designs
White Electronic Designs


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