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WV3HG128M72AER-AD6 の電気的特性と機能

WV3HG128M72AER-AD6のメーカーはWhite Electronic Designsです、この部品の機能は「1GB - 128Mx72 DDR2 SDRAM RDIMM」です。


製品の詳細 ( Datasheet PDF )

部品番号 WV3HG128M72AER-AD6
部品説明 1GB - 128Mx72 DDR2 SDRAM RDIMM
メーカ White Electronic Designs
ロゴ White Electronic Designs ロゴ 




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WV3HG128M72AER-AD6 Datasheet, WV3HG128M72AER-AD6 PDF,ピン配置, 機能
White Electronic Designs WV3HG128M72AER-AD6
ADVANCED*
1GB – 128Mx72 DDR2 SDRAM RDIMM, VLP
FEATURES
VLP (very low profile) 240-pin, dual in-line memory
module
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4300 and PC2-3200
Utilizes 800*, 667*, 533 and 400 Mb/s DDR2
SDRAM components
VCC = VCCQ = 1.8V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5* and 6*
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
Auto &self refresh (64ms: 8,192 cycle refresh)
wwwG.DoaltdaSehdegeet4cUo.ncotamcts
RoHS compliant
Package option
• 240 Pin DIMM VLP
• PCB – 18.29mm (0.720") Max
DESCRIPTION
The WV3HG128M72AER is a 128Mx72 Double Data Rate
DDR2 SDRAM high density module. This memory module
consists of eighteen 128Mx4 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
VLP 240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4300
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
March 2005
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 Page





WV3HG128M72AER-AD6 pdf, ピン配列
White Electronic Designs WV3HG128M72AER-AD6
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
VSS
RS0#
DQS0
DQS0#
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1#
DQ8
DQ9
DQ10
DQ11
DQS2
DQS2#
DQ16
DQ17
DQ18
DQ19
DQS3
DQS3#
DQ24
DQ25
DQ26
DQ27
DQS4
DQS4#
DQ32
DQ33
DQ34
DQ35
DQS5
DQS5#
DQ40
DQ41
DQ42
DQ43
DQS6
DQS6#
DQ48
DQ49
DQ50
www.DataSheet4U.DcQ5o1 m
DQS7
DQS7#
DQ56
DQ57
DQ58
DQ59
DQS8
DQS8#
CB0
CB1
CB2
CB3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM0/DQS9
NC/DQS9#
DQ4
DQ5
DQ6
DQ7
DM1/DQS10
NC/DQS10#
DQ12
DQ13
DQ14
DQ15
DM2/DQS11
NC/DQS11#
DQ20
DQ21
DQ22
DQ23
DM3/DQS12
NC/DQS12#
DQ28
DQ29
DQ30
DQ31
DM4/DQS13
NC/DQS13#
DQ36
DQ37
DQ38
DQ39
DM5/DQS14
NC/DQS14#
DQ44
DQ45
DQ46
DQ47
DM6/DQS15
NC/DQS15#
DQ52
DQ53
DQ54
DQ55
DM7/DQS16
NC/DQS16#
DQ60
DQ61
DQ62
DQ63
DM8/DQS17
NC/DQS17#
CB4
CB5
CB6
CB7
DM CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
SCL
VCCSPD
VCC/VCCQ
VREF
VSS
Serial PD
WP A0 A1 A2
SA0 SA1 SA2
SDA
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
S0#
BA0 - BA1
A0 - A13
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
1:2
R
E
G
I
S
T
E
R
RST#
RS0# : DDR2 SDRAMs
RBA0 - RBA1 : DDR2 SDRAMs
RA0 - RA13 : DDR2 SDRAMs
RRAS# : DDR2 SDRAMs
RCAS# : DDR2 SDRAMs
RWE# : DDR2 SDRAMs
RCKE0 : DDR2 SDRAMs
RODT0 : DDR2 SDRAMs
PCK7
PCK7#
NOTE: All resistor values are 22 ohms unless otherwise specified.
CK0
CK0#
RESET#
P
L
L
OE
PCK0-PCK6, PCK8, PCK9 CK : DDR2 SDRAMs
PCK0#-PCK6#, PCK8#, PCK9#
PCK7 CK : Register
PCK7# CK# : Register
CK# : DDR2 SDRAMs
March 2005
Rev. 1
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com


3Pages


WV3HG128M72AER-AD6 電子部品, 半導体
White Electronic Designs WV3HG128M72AER-AD6
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
VCC = +1.8V ± 0.1V
Symbol
ICC0
ICC1
ICC2P
ICC2Q
ICC2N
ICC3P
Proposed Conditions
Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC);
CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as IDAD6W
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
ICC3N Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDAD6W
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP
= tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
wwIDwAD.6DRataSOhpeereatt4inUg .bcuorsmt read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDAD6W
ICC5B Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
ICC6 Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
ICC7 Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC =
tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for
detailed timing conditions
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different.
534
2,420
2,640
784
1,110
1,090
1,190
600
1,840
3,820
3,590
4,150
99
5,900
403
2,250
2,400
724
1,040
1,130
1,190
570
1,730
2,900
3,000
3,880
99
5,570
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
March 2005
Rev. 1
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page



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部品番号部品説明メーカ
WV3HG128M72AER-AD6

1GB - 128Mx72 DDR2 SDRAM RDIMM

White Electronic Designs
White Electronic Designs


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