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WV3EG265M64EFSU-D4 の電気的特性と機能

WV3EG265M64EFSU-D4のメーカーはWhite Electronic Designsです、この部品の機能は「1GB- 2x64Mx64 DDR SDRAM UNBUFFERED」です。


製品の詳細 ( Datasheet PDF )

部品番号 WV3EG265M64EFSU-D4
部品説明 1GB- 2x64Mx64 DDR SDRAM UNBUFFERED
メーカ White Electronic Designs
ロゴ White Electronic Designs ロゴ 




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WV3EG265M64EFSU-D4 Datasheet, WV3EG265M64EFSU-D4 PDF,ピン配置, 機能
White Electronic Designs WV3EG265M64EFSU-D4
1GB – 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL
FEATURES
Double-data-rate architecture
PC2700 and PC2100
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2, 2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power supply: VCC/VCCQ: 2.5V ± 0.2V
Dual Rank
200 pin SO-DIMM package
• Package height options:
D4: 31.75 mm (1.25”)
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
DESCRIPTION
The WV3EG265M64EFSU is a 2x64Mx64 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM component. The module consists of sixteen
64Mx8 bit with 4 banks DDR SDRAMs in FBGA packages
mounted on a 200 pin substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is subject to change without notice.
www.DataSheet4U.com
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
October 2005
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 Page





WV3EG265M64EFSU-D4 pdf, ピン配列
White Electronic Designs WV3EG265M64EFSU-D4
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
www.DataSheet4U.com
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS S0#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S0#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S0#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S0#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S1#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S1#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S1#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S1#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS S0#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S0#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S0#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S0#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S1#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S1#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S1#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS S1#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
BA0-BA1
A0-A12
RAS#
CAS#
WE#
CS1#
CS0#
VCCSPD
VCC/VCCQ
VREF
VSS
BA0-BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
WE#: DDR SDRAMs
CS1#: DDR SDRAMs
CS0#: DDR SDRAMs
CK0
CK0#
SPD
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
PLL
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
SERIAL PD
SCL
SDA
WP A0 A1 A2
SA0 SA1 SA2
NOTE: All datalines are terminated through a 22 ohm series resistor
October 2005
Rev. 1
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com


3Pages


WV3EG265M64EFSU-D4 電子部品, 半導体
White Electronic Designs WV3EG265M64EFSU-D4
AC TIMING PARAMETERS
0 ≤ TA ≤ 70°C, VCC = 2.5V, VCCQ = 2.5V
Parameter
Row cycle time
Refresh row cycletime
Row active time
RAS# to CAS# delay
Row precharge time
Row active to Rowactivedelay
Write recovery time
Last data into Read command
Clock cycle time
Clock high leve width
Clock low level width
DQS-out access time from CK/CK#
Output data access time from CK/CK#
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
wAwddwre.DssaatnadSChoenetrto4lUIn.pcuotmsetup time (fast)
Address and Control Input hold time (fast)
Address and Control Input setup time (slow)
Address and Control Input hold time (slow)
Data-out high impedence time from CK/CK#
Data-out low impedence time from CK/CK#
Symbol
CL=2.0
CL=2.5
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tISF
tISHF
tISS
tIHS
tHZ
tLZ
335
Min Max
60
72
42 70K
15
15
12
15
1
7.5 13
6 13
0.45 0.55
0.55 0.55
-0.6 +0.6
-0.7 +0.7
— 0.45
0.9 1.1
0.4 0.6
0.75 1.25
0
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.8
0.8
+0.7
-0.7
262
Min Max
65
75
40 120K
20
20
15
15
1
7.5 13
7.5 13
0.45 0.55
0.55 0.55
-0.75 +0.75
-0.75 +0.75
— 0.5
0.9 1.1
0.4 0.6
0.75 1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
1
1
+0.75
-0.75
Note:
AC Timing Parameters are based on Micron components. Other DRAM Manufacturers parameters may be different.
265
Min Max
65
75
40 120K
20
20
15
15
1
10 13
7.5 13
0.45 0.55
0.55 0.55
-0.75 +0.75
-0.75 +0.75
— 0.5
0.9 1.1
0.4 0.6
0.75 1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
1
1
+0.75
-0.75
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
October 2005
Rev. 1
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page



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部品番号部品説明メーカ
WV3EG265M64EFSU-D4

1GB- 2x64Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
White Electronic Designs


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