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PDF IS41C85125 Data sheet ( Hoja de datos )
| Número de pieza | IS41C85125 | |
| Descripción | 512K x 8 (4-MBIT) DYNAMIC RAM | |
| Fabricantes | Integrated Silicon Solution | |
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IS41C85125
IS41LV85125
ISSI ®
512K x 8 (4-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
PRELIMINARY INFORMATION
AUGUST 2001
www.datasheet4u.com
FEATURES
• Fast access and cycle time
• TTL compatible inputs and outputs
• Refresh Interval: 1024 cycles/16 ms
• Refresh Mode: RAS-Only, CAS-before-RAS
(CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
-- 5V ± 10% (IS41C85125)
-- 3.3V ± 10% (IS41LV85125)
• Industrial temperature available
DESCRIPTION
The ISSI IS41C85125 and IS41LV85125 are 512,288 x 8-bit
high-performance CMOS Dynamic Random Access
Memories. Fast Page Mode allows 1024 random accesses
within a single row with access cycle time as short as 12
ns per 8-bit word.
These features make the IS41C85125 and the IS41LV85125
ideally suited for high band-width graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IS41C85125 and IS41LV85125 are available in a
28-pin, 400-mil SOJ package.
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. Fast Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
-35
35
10
18
12
60
-60 Unit
60 ns
15 ns
30 ns
25 ns
110 ns
PIN DESCRIPTIONS
A0-A9
I/O0-I/O7
WE
OE
RAS
CAS
VCC
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
PIN CONFIGURATION
28-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
NC
WE
RAS
A9
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 GND
27 I/O7
26 I/O6
25 I/O5
24 I/O4
23 CAS
22 OE
21 NC
20 A8
19 A7
18 A6
17 A5
16 A4
15 GND
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/25/01
1
1 page  
IS41C85125
IS41LV85125
ISSI ®
ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max. Unit
IIL Input Leakage Current
www.datasheet4u.com
IIO Output Leakage Current
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
–10 10
–10 10
µA
µA
VOH Output High Voltage Level
IOH = –2.5 mA
2.4 —
V
VOL Output Low Voltage Level
IOL = 2.1 mA
— 0.4 V
ICC1 Stand-by Current: TTL
RAS, CAS ≥ VIH
5V Com.
5V Ind.
3.3V Com.
3.3V Ind.
— 2 mA
—3
—1
—2
ICC2 Stand-by Current: CMOS
RAS, CAS ≥ VCC – 0.2V 5V
3.3V
— 2 mA
—1
ICC3 Operating Current:
RAS, CAS,
Random Read/Write(2,3,4)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
-35 — 230 mA
-60 — 170
ICC4 Operating Current:
RAS = VIL, CAS,
Fast Page Mode(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
-35 — 220 mA
-60 — 160
ICC5 Refresh Current:
RAS-Only(2,3)
RAS Cycling, CAS ≥ VIH
tRC = tRC (min.)
Average Power Supply Current
-35 — 230 mA
-60 — 170
ICC6 Refresh Current:
RAS, CAS Cycling
CBR(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
-35 — 230 mA
-60 — 170
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured.The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each fast page cycle.
5. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/25/01
5
5 Page 
IS41C85125
IS41LV85125
FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE)
www.datasheet4u.com RAS
tCRP
CAS
tASR
ADDRESS
Row
WE
I/O
tRAS
tRC
tRCD
tCSH
tRSH
tCAS tCLCH
tRAD
tRAH
tASC
tAR
tRAL
tCAH
tACH
Column
tWCR
tWCS
tCWL
tRWL
tWCH
tWP
tDHR
tDS
tDH
Valid Data
ISSI ®
tRP
Row
Don't Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/25/01
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet IS41C85125.PDF ] | |
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