PDF NB3N3011 Data sheet ( Hoja de datos )

Número de pieza	NB3N3011
Descripción	PureEdge Clock Generator
Fabricantes	ON Semiconductor
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No Preview Available ! www.DataSheet4U.com NB3N3011 3.3 V 100 MHz / 106.25 MHz PureEdge Clock Generator with LVPECL Differential Output Description The NB3N3011 is a Fibre Channel Clock Generator and uses a 26.5625 MHz crystal to synthesize 106.25 MHz or a 25 MHz crystal to synthesize 100 MHz. The NB3N3011 has excellent <1 ps phase jitter performance over the 637 kHz – 10 MHz integration range. The NB3N3011 is packaged in an 8−Pin 4.4 mm x 3.0 mm TSSOP, making it ideal for use in systems with limited board space. Features • PureEdge Clock Family Provides Accuracy and Precision • One Differential LVPECL Output • Crystal Oscillator Interface Designed for Fundamental Mode 18 pF Parallel Resonant Crystal (25 MHz or 26.5625 MHz) • Output Frequency: 106.25 MHz (26.5625 MHz Crystal) or 100 MHz (25 MHz Crystal) • VCO Range: 760 MHz − 950 MHz • RMS Phase Jitter @ 100 MHz, using a 25 MHz Crystal (637 kHz − 10 MHz): 0.29 ps (Typical) • RMS Phase Noise at 106.25 MHz Phase noise: Offset Noise Power 100 Hz −108 dBc/Hz 1 kHz −122 dBc/Hz 10 kHz −135 dBc/Hz 100 kHz −135 dBc/Hz • 3.3 V Power Supply • −40°C to 85°C Ambient Operating Temperature • These are Pb−Free Devices* http://onsemi.com MARKING DIAGRAM TSSOP−8 DT SUFFIX CASE 948S 311 YWW AG A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. 25 MHz XIN or 26.5625 MHz XOUT Crystal Oscillator Phase Detector Charge Pump M = B32 VCO 850 MHz w/26.5625 MHz Ref. N =B8 LVPECL Output Q 100 MHz or Q 106.25 MHz Figure 1. Logic Diagram *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 0 1 Publication Order Number: NB3N3011/D 1 page NB3N3011 APPLICATION INFORMATION Power Supply Filtering The NB3N3011 is a mixed analog/digital product, and as such, it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The NB3N3011 also generates sub−nanosecond output edge rates, and therefore, a good power supply bypassing scheme is a must. The NB3N3011 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCCA). The simplest form of noise isolation is a power supply filter on the VCCA pin. Figure 8 illustrates a typical power supply filter scheme. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. The purpose of this design technique is to try and isolate the high switching noise of the digital outputs from the relatively sensitive internal analog phase−locked loop. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise−related problems in most designs. Crystal Oscillator Input Interface The NB3N3011 features an integrated crystal oscillator to minimize system implementation costs. The oscillator circuit is a parallel resonant circuit and thus, for optimum performance, a parallel resonant crystal should be used. As the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the NB3N3011 as possible to avoid any board level parasitics. Surface mount crystals are recommended, but not required. Figure 9 illustrates a parallel resonant crystal with its associated load capacitors. The capacitor values shown were determined using a 26.5625 MHz, 18 pF parallel resonant crystal and were chosen to minimize the ppm error. Capacitor values can be adjusted slightly for different board layouts to optimize accuracy. 3.3 V VCC 0.01 mF 10 W VCCA 0.01 mF 10 mF Figure 8. Power Supply Filtering X1 18 pFParallel Crystal C1 33 pF XOUT C2 27 pF XIN Figure 9. Crystal Input Interface APPLICATION SCHEMATIC Figure 10 shows a schematic example of the NB3N3011. An example of LVPECL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the AND8020 Application Note. In this example, an 18 pF parallel resonant 26.5625MHz crystal is used for generating 106.25 MHz output frequency. The C1 = 27 pF and C2 = 33 pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. VCC R2 10 10 C3 mF C2 33 pF 18 pF VCCA C4 0.01 mF X1 U1 1 2 3 4 VCCA VEE XOUT XIN VCC Q Q NC 8 7 6 5 VCC VCC R3 Q ZO = 50 W 133 R5 133 Q ZO = 50 W + − C1 27 pF VCC = 3.3 V C5 0.1 m 82R.45 R826.5 Figure 10. Typical Application Schematic http://onsemi.com 5 5 Page

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