PDF ICS93705 Data sheet ( Hoja de datos )

Número de pieza	ICS93705
Descripción	DDR Phase Lock Loop Zero Delay Clock Buffer
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. ICS9370 5 DDR Phase Lock Loop Zero Delay Clock Buffer Recommended Application: DDR Zero Delay Clock Buffer Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • PEAK - PEAK jitter (66MHz): <120ps • PEAK - PEAK jitter (>100MHz): <75ps • CYCLE - CYCLE jitter (66MHz):<120ps • CYCLE - CYCLE jitter (>100MHz):<65ps • OUTPUT - OUTPUT skew: <100ps • Output Rise and Fall Time: 450ps - 950ps • DUTY CYCLE: 49% - 51% Pin Configuration GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD SCLK CLK_INT N/C VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 GND 47 CLKC5 46 CLKT5 45 VDD 44 CLKT6 43 CLKC6 42 GND 41 GND 40 CLKC7 39 CLKT7 38 VDD 37 SDATA 36 N/C 35 FB_INT 34 VDD 33 FB_OUTT 32 N/C 31 GND 30 CLKC8 29 CLKT8 28 VDD 27 CLKT9 26 CLKC9 25 GND 48-Pin SSOP Block Diagram SCLK SDATA Control Logic FB_INT CLK_INT PLL FB_OUTT CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 Functionality INPUTS OUTPUTS AVDD CLK_INT CLKT CLKC FB_OUTT 2.5V (nom) L LH L 2.5V (nom) H HL H 2.5V (nom) <20MHz(1) Z Z Z GND L LH L GND H HL H PLL State on on off Bypassed/off Bypassed/off 0418C—08/08/02 1 page ICS9370 5 Recommended Operating Condition TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX Analog/core supply voltage VDD, AVDD 2.3 2.5 2.7 Input voltage level Input duty cycle Input max jitter VIL VIH IDC ITCYC - VDD/2 + 0.5V 40 VDD/2 - 0.5V - 60 500 UNITS V V V % ps Timing Requirements TA = 0 - 70C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Operating Clock Frequency1 Input Clock Duty Cycle1 Clock Stabilization1 freqop dtin tSTAB from VDD = 2.5V to 1% target frequency 1. Guaranteed by design, not 100% tested in production. MIN 66 40 TYP MAX UNITS 170 MHz 60 % 100 µs Switching Characteristics TA = 0 - 70C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Absolute Jitter1 tjabs 66 MHz 100 / 125 / 133 / 167 MHz Cycle to cycle Jitter1,2 Phase Error1 Output to output Skew1 tc-c tpe Ts k ew 66 MHz 100 / 125 / 133 / 167 MHz with input clock 0-2.5V 0.8ns rise/fall with input clock 0-2.5V 0.8ns rise/fall -150 50 35 50 40 Low-to-high level Propagation Delay Time, Bypass Mode1 tPLH CLK_IN to any output, Load = 120W / 12 pF 4 4.5 Pulse Skew1 Duty Cycle (differential)1,3 Rise Time, Fall Time1 Tskewp DC tR, tF no loads, 66 MHz to 167 MHz 49 Single-ended 20 - 80 %; Load = 120Ω / 12 pF 450 50 550 1. Guaranteed by design, not 100% tested in production. 2. Refers to transistion on non-inverting period. 3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = twH / tC, where the cycle time (tC) decreases as the frequency increases. MAX 120 75 110 65 150 100 UNITS ps ps ps ps 6 ns 100 ps 51 % 950 ps 0418C—08/08 /02 5 5 Page

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