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PDF MTP5N40E Data sheet ( Hoja de datos )
| Número de pieza | MTP5N40E | |
| Descripción | TMOS POWER FET 5.0 AMPERES 400 VOLTS RDS(on) = 1.0 OHM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTP5N40E/D
™Designer's Data Sheet
TMOS E-FET.™
High Energy Power FET
N–Channel Enhancement–Mode Silicon Gate
This advanced high voltage TMOS E–FET is designed to
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a drain–to–source diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
• Avalanche Energy Capability Specified at Elevated
Temperature
• Low Stored Gate Charge for Efficient Switching
• Internal Source–to–Drain Diode Designed to Replace External
Zener Transient Suppressor — Absorbs High Energy in the
Avalanche Mode
• Source–to–Drain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode
G
®
D
S
MTP5N40E
Motorola Preferred Device
TMOS POWER FET
5.0 AMPERES
400 VOLTS
RDS(on) = 1.0 OHM
CASE 221A–06, Style 5
TO–220AB
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–repetitive
VDSS
VDGR
VGS
VGSM
400 Vdc
400 Vdc
± 20 Vdc
± 40 Vpk
Drain Current — Continuous
Drain Current — Pulsed
ID 5.0 Adc
IDM 12
Total Power Dissipation @ TC = 25°C
Derate above 25°C
PD 75 Watts
0.6 W/°C
Operating and Storage Temperature Range
TJ, Tstg
– 55 to 150
°C
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C)
Single Pulse Drain–to–Source Avalanche Energy — TJ = 25°C
Single Pulse Drain–to–Source Avalanche Energy — TJ = 100°C
Repetitive Pulse Drain–to–Source Avalanche Energy
WDSR (1)
WDSR (2)
290
46
7.4
mJ
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient°
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) VDD = 50 V, ID = 5.0 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response
RθJC
RθJA
TL
1.67 °C/W
62.5
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1
1 page  
2000
1500
1000 Crss
TJ = 25°C
VGS = 0
Ciss
16
TJ = 25°C
ID = 5 A
12
8
MTP5N40E
VDS = 100 V
320 V
200 V
500
VDS = 0 V
Coss
0
10 5 0 5 10 15 20 25
VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 11. Capacitance Variation
4
0
0 10
20 30
40 50
Qg, TOTAL GATE CHARGE (nC)
Figure 12. Gate Charge versus
Gate–To–Source Voltage
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of
Figure 14 defines the limits of safe operation for commutated
source–drain current versus re–applied drain voltage when
the source–drain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VDS for a given
rate of change of source current. It is applicable when wave-
forms similar to those of Figure 11 are present. Full or half–
bridge PWM DC motor controllers are common applications
requiring CSOA data.
Device stresses increase with increasing rate of change of
source current so dIs/dt is specified with a maximum value.
Higher values of dIs/dt require an appropriate derating of IFM,
peak VDS or both. Ultimately dIs/dt is limited primarily by de-
vice, package, and circuit impedances. Maximum device
stress occurs during trr as the diode goes from conduction to
reverse blocking.
VDS(pk) is the peak drain–to–source voltage that the device
must sustain during commutation; IFM is the maximum for-
ward source–drain diode current just prior to the onset of
commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.
6
Stray inductances in Motorola’s test circuit are assumed to
be practical minimums. dVDS/dt in excess of 10 V/ns was at-
tained with dIs/dt of 400 A/µs.
15 V
VGS
0
90%
IS
10%
IFM dls/dt
trr
ton IRM
0.25 IRM
VDS(pk)
VDS
dVDS/dt
Vf VdsL
VR
MAX. CSOA
STRESS AREA
Figure 15. Commutating Waveforms
RGS DUT
4
di/dt ≤ 90 A/µs
2
0
0 100 200 300 400 500
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 13. Commutating Safe Operating Area (CSOA)
–
VR
+
VGS
IFM
+
IS
VDS
20 V
–
Li
VR = 80% OF RATED VDS
VdsL = Vf + Li ⋅ dls/dt
Figure 14. Commutating Safe Operating Area
Test Circuit
Motorola TMOS Power MOSFET Transistor Device Data
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MTP5N40E.PDF ] | |
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