PDF HYS72D64000GU-7-A Data sheet ( Hoja de datos )

Número de pieza	HYS72D64000GU-7-A
Descripción	2.5 V 184-pin Unbuffered DDR-I SDRAM Modules
Fabricantes	Infineon
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No Preview Available ! HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules 512 MByte & 1024 MByte Modules PC1600, PC2100 & PC2700 Preliminary datasheet rev. 0.81 • 184-pin Unbuffered 8-Byte Dual-In-Line • Auto Refresh (CBR) and Self Refresh DDR-I SDRAM non-parity and ECC-Modules for PC and Server main memory applications • All inputs and outputs SSTL_2 compatible • One bank 64M x 64, 64M x 72 and two bank • Serial Presence Detect with E2PROM 128M x 64, 128M × 72 organization • Jedec standard MO-206 form factor: • JEDEC standard Double Data Rate 133.35 mm × 31.75 mm × 4.00 mm max. Synchronous DRAMs (DDR-I SDRAM) • Jedec standard reference layout Single + 2.5 V (± 0.2 V) power supply • Gold plated contacts • Built with 512 Mbit DDR-I SDRAMs organized as 64Mb x 8 in 66-Lead TSOPII package • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • Performance: Component Speed Grade Module Speed Grade fCK Clock Frequency (max.) @ CL = 2.5 fCK Clock Frequency (max.) @ CL = 2 -6 -7 -8 DDR333B DDR266A DDR200 PC2700 PC2100 PC1600 166 143 125 133 133 100 Unit MHz MHz The HYS64/72D64000GU and HYS64/72D128020GU are industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs) organized as 64M × 64 and 128M × 64 for non-parity and 64M x 72 and 128M x 72 for ECC main memory applications. The memory array is designed with 512Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. INFINEON Technologies 1 2002-09-10 (rev.0.81) 1 page HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 S0 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D0 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D1 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D2 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D3 DQS4 DM4/DQS13 DQS5 DM5/DQS14 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS6 DM6/DQS15 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS7 DM7/DQS16 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 BA0 - BA1 A0 -A11, A12 VDD, VDDQ VREF VSS VDDID Serial PD SCL A0 A1 A2 SDA SA0 BA0, BA1: SDRAMs D0 - D7 A0 - A11,A12: SDRAMs D0 - D7 SA1 D0 - D7 D0 - D7 D0 - D7 RAS CAS CKE0 WE SA2 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 CKE: SDRAMs D0 - D7 WE : SDRAMs D0 - D7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D4 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D5 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D6 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D7 * Clock Wiring Clock Input SDRAMs CK0/CK0 CK1/CK1 CK2/CK2 2 SDRAMs 3 SDRAMs 3 SDRAMs Wire per Clock Loading Table/W iring Diagrams Notes: 1. DQ-to-I/O wiring is shown as recom- mended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ Block Diagram: One Bank 64M x 64 DDR-I SDRAM DIMM Module HYS64D64000GU using x8 organized SDRAMs INFINEON Technologies 5 2002-09-10 (rev.0.81) 5 Page HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules Operating, Standby and Refresh Currents (PC1600) Symbol Parameter/Condition 512MB x64 1bank -8 512MB x72 1bank -8 1GB x64 2bank -8 1GB x72 2bank -8 Notes Unit MAX MAX MAX MAX 4 Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK = IDD0 tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles 1280 1440 1680 1890 mA 1 IDD1 Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page for detailed test conditions. 1360 1530 1760 1980 mA 1, 3 IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE <= VIL MAX; tCK = tCK MIN 96 108 192 216 mA 2 Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; IDD2F CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs 320 360 640 720 mA 2 changing once per clock cycle, VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle; IDD2Q CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs 200 225 400 450 mA 2 stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM. Active Power-Down Standby Current: one bank active; power-down IDD3P mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and 128 144 256 288 mA 2 DM. Active Standby Current: one bank active; active / precharge;CS >= VIH MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and IDD3N DQS inputs changing twice per clock cycle; address and control inputs 400 450 800 900 mA 2 changing once per clock cycle Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data IDD4R outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA 1320 1485 1720 1935 mA 1, 3 Operating Current: one bank active; Burst = 2; writes; continuous burst; IDD4W address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN 1280 IDD5 Auto-Refresh Current: tRC = tRFC MIN, distributed refresh IDD6 Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN 2320 40 IDD7 Operating Current: four bank; four bank interleaving with BL=4; Refer to the following page for detailed test conditions. 2800 1440 2610 45 3150 1680 2720 80 3200 1890 mA 3060 90 mA mA 3600 mA 1 1 1, 3 1. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for two bank modules (n: number of components per module bank) 3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C INFINEON Technologies 11 2002-09-10 (rev.0.81) 11 Page

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