PDF HV7351K6-G Data sheet ( Hoja de datos )

Número de pieza	HV7351K6-G
Descripción	Eight Channel Programmable High Voltage Ultrasound Transmit Beamformer
Fabricantes	Supertex
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No Preview Available ! Supertex inc. HV7351 Eight Channel Programmable High Voltage Ultrasound Transmit Beamformer Features ►► Eight channels with return to zero ►► Up to ±70V output voltage ►► ±3.0A output current ►► Store up to four different patterns ►► Independent programmable delays ►► Single 11x11 QFN-80 package Application ►► Medical ultrasound imaging ►► NDT, non-destructive testing ►► Arbitrary pattern generator ►► High speed PIN diode driver General Description The Supertex HV7351 is an 8-channel programmable high voltage ultrasound transmit beamformer. Each channel is capable of swinging up to ±70V with an active discharge back to 0V. The outputs can source and sink more than 3.0A to achieve fast output rise and fall times. The active discharge is also capable of sourcing and sinking 3.0A for a fast return to ground. The topology of the HV7351 will significantly reduce the number of I/O logic control lines needed. Each pulser has four associated 64-bit shift registers for storing pre-determined transmit patterns and a 10-bit delay counter for controlling the transmit time. One of four arbitrary patterns can be transmitted with adjustable delay, depending on the data loaded into these shift registers and the delay counter. The delay counter can be clocked up to 200MHz, allowing incremental delays down to 5ns. Typical Application Circuit HV7351 8-channel U1 Tx1 Tx2 Trigger HV7351 8-channel U2 Tx3 tDELAY1 tDELAY2 tDELAY3 Array Probe E1 E2 E3 HV7351 8-channel U16 Tx127 Tx128 Doc.# DSFP-HV7351 NR050213 Trigger tDELAY127 tDELAY128 E127 E128 Supertex inc. www.supertex.com 1 page HV7351 AC Electrical Characteristics (cont.) (Operating conditions unless otherwise specified, VLL =3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC) Sym Parameter Min Typ Max Units Conditions tdr1 Output propagation delay rise time 1 10.85 13.35 15.85 tdf1 Output propagation delay fall time 1 11.35 13.85 16.35 tdr2 Output propagation delay rise time 2 tdf2 Output propagation delay fall time 2 11.25 11.75 13.75 14.25 16.25 16.75 ns No Load. tdr3 Output propagation delay rise time 3 11.35 13.85 16.35 tdf3 Output propagation delay fall time 3 11.45 13.95 16.45 tdcwlh CW output propagation delay time from low to high tdcwhl CW output propagation delay time from high to low 10.45 10.35 12.95 12.85 15.45 15.35 ns VPP = +5.0V, VNN = -5.0V, No Load Δtdcwhl tJCW LAT Delay time matching Delay jitter on rise or fall Latency - - 3.5TCK ±0.7 13 3.5TCK - - 3.5TCK ns P to N, channel-to-channel matching ps VPP = +5.0V, VNN = -5.0V, Load = 50Ω - --- Output P-channel MOSFET to VPP, CW = 0 IOUT Output saturation current 2.2 3.2 - A --- RON Output ON-resistance - 4.2 - Ω IOUT = 100mA COSS Output capacitance - 62 - pF VPP - VOUT = 25V, f = 1.0MHz Output N-channel MOSFET to VNN, CW = 0 IOUT Output saturation current - -3.2 -2.2 A --- RON Output ON-resistance - 2.4 - Ω IOUT = -100mA COSS Output capacitance - 50 - pF VNN - VOUT = -25V, f = 1.0MHz Output P-channel MOSFET to VPP, CW = 1 IOUT Output saturation current 1.2 1.5 - A --- RON Output ON-resistance - 8.0 - Ω IOUT = 100mA COSS Output capacitance - 62 - pF VPP - VOUT = 25V, f = 1.0MHz Output N-channel MOSFET to VNN, CW = 1 IOUT Output saturation current - -1.5 -1.2 A --- RON Output ON-resistance - 6.6 - Ω IOUT = -100mA COSS Output capacitance - 50 - pF VNN - VOUT = -25V, f = 1.0MHz Doc.# DSFP-HV7351 NR050213 Supertex inc. 5 www.supertex.com 5 Page HV7351 Loading Data into the Delay Counters and the Divide-by-N Counter Each output channel, TX, has its own programmable 10-bit delay counter. For 8 channels, 80 bits are needed. A 6-bit divide-by-N counter is also provided to program the desired TX frequency. To program all the individual delay counters and the divide-by-N counter, an 86-bit serial shift register is provided. It uses the same clock input that the pattern registers uses. DIN2 is the input data for this register. When CS2 is high, data will not be shifted in. Data is shifted in only when CS2 is low. though to the 6-bit register for the divide by N counter. Data is clocked in during the rising edge of the clock. There is no activity during the falling edge of the clock. The MSB bit in the 6-bit divide-by-N register is clocked out into DOUT2 for cascading multiple devices if desired. 10-Bit Delay Counter The input clock for the 10-bit delay counter is the TCK pin. The TCK pin is the only pin that is capable of high frequency, 200MHz. This helps maximum delay time resolution. The counter counts upward. Please refer to the table below. As shown below, the data first enters into the 10-bit regis- ter for the TX8 delay counter and continues to be shifted DIN2 SCK 86-bit Serial Shift Register: 80 bits for the delay counters and 6 bits for the divide by N 10 bits Tx8 10 bits Tx7 10 bits Tx6 10 bits Tx5 10 bits Tx4 10 bits Tx3 10 bits Tx2 10 bits Tx1 6 bits divide by N DOUT2 10 bits for Tx8 delay Counter 10 bits for Tx7 delay Counter 6 bits for divide by N S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 LSB MSB LSB MSB S6 S5 S4 S3 S2 S1 LSB MSB Delay Counter Table MSB LSB 0000000000 0000000001 0000000010 0000000011 IIIIIIIIII IIIIIIIIII IIIIIIIIII 1111111100 1111111101 1111111110 1111111111 Delay Time 1023 TCK cycles 1022 TCK cycles 1021 TCK cycles 1020 TCK cycles I I I 3 TCK cycles 2 TCK cycles 1 TCK cycle No trigger Doc.# DSFP-HV7351 NR050213 Supertex inc. 11 www.supertex.com 11 Page

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