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PDF HV7351 Data sheet ( Hoja de datos )
| Número de pieza | HV7351 | |
| Descripción | 3A Programmable High-Voltage Ultrasound-Transmit Beamformer | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HV7351 (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
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HV7351
8-Channel, ±70V, 3A Programmable High-Voltage
Ultrasound-Transmit Beamformer
Features
• Eight Channels with Return-to-Zero (RTZ)
• Up to ±70V Output Voltage
• ±3.0A Output Current
• Stores up to Four Different Patterns
• Independent Programmable Delays
• 80-lead Single 11 x 11 mm VQFN Package
Applications
• Medical Ultrasound Imaging
• NDT, Non-Destructive Testing
• Arbitrary Pattern Generator
• High-Speed PIN Diode Driver
Typical Application Circuit
HV7351
8-channel
U1
Tx1
Tx2
tDELAY1
tDELAY2
General Description
The HV7351 device is an 8-channel programmable
high-voltage ultrasound-transmit beamformer. Each
channel is capable of swinging up to ±70V with an
active discharge back to 0V. The outputs can source
and sink up to 3.0A to achieve fast output rise and fall
times. The active discharge is also capable of sourcing
and sinking 3.0A for a fast return to ground. The topol-
ogy of the HV7351 will significantly reduce the number
of I/O logic control lines needed.
Each pulser has four associated 64-bit shift registers
for storing predetermined transmit patterns and a 10-bit
delay counter for controlling the transmit time. One of
four arbitrary patterns can be transmitted with adjust-
able delay, depending on the data loaded into these
shift registers and the delay counter. The delay counter
can be clocked up to 200 MHz, allowing incremental
delays down to 5 ns.
Array
Probe
E1
E2
TRIG
HV7351
8-channel
U2
Tx3
tDELAY3
E3
HV7351
8-channel
U16
Tx127
Tx128
TRIG
tDELAY127
tDELAY128
2015 Microchip Technology Inc.
E127
E128
DS20005412A-page 1
1 page  
HV7351
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Positive logic supply (VLL)............................................................................................................................ -0.5V to 5.5V
Positive logic supply voltage (DVDD)............................................................................................................ -0.5V to 5.5V
Positive gate drive supply voltage (PVDD) ................................................................................................... -0.5V to 5.5V
Positive analog supply voltage (AVDD)......................................................................................................... -0.5V to 5.5V
Negative gate drive supply voltage (PVSS) ................................................................................................ +0.5V to -5.5V
High-voltage positive supply voltage (VPP) ................................................................................................. -0.5V to +80V
High-voltage negative supply voltage (VNN) ............................................................................................... +0.5V to -80V
Differential high voltage supply (VPP - VNN)............................................................................................................+160V
Positive floating supply voltage (VPF) .................................................................................................. VPP – 6.0V to VPP
Negative floating supply voltage (VNF).................................................................................................VNN to VNN + 6.0V
Positive supply for VNF regulator (VRP)............................................................................................................. 0V to 15V
Negative supply for VPF regulator (VRN) .......................................................................................................... 0V to -15V
Operating temperature ...........................................................................................................................-40°C to +125°C
Storage temperature ...............................................................................................................................-65°C to +150°C
ESD Rating All Pins .............................................................................................................................................. 0.75 kV
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods
may affect device reliability.
TABLE 1-1: OPERATING SUPPLY VOLTAGES
Electrical Specifications: Unless otherwise specified: TA = +25°C. Boldface specifications apply over the TA range
of -20 to +85°C.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Positive High Voltage Supply
Negative High Voltage Supply
Logic Interface Voltage
Low-Voltage Positive Analog
Supply Voltage
Low-Voltage Positive Digital
Supply Voltage
Low-Voltage Positive Gate Drive
Supply Voltage
Low-Voltage Negative Gate
Drive Supply Voltage
Low-Voltage Positive Supply
for VNF Regulator
Low-Voltage Negative Supply
for VPF Regulator
Reference Voltage Logic Trip
Point for TCK Pin
VPP
VNN
VLL
AVDD
DVDD
PVDD
PVSS
VRP
VRN
TCK
3.0
-70
2.85
4.75
4.75
4.75
-5.25
4.75
-12
0.4VLL
—
—
3.30
5.00
5.00
5.00
-5.00
—
—
0.5VLL
70
-3.0
3.6
5.25
5.25
5.25
-4.75
12
-4.75
0.6VLL
V Note 1
V
V
V
V
V
V
V
V
V
TCK/TCK Input Current
ITCK/ITCK
—
— ±10
Note 1: Specification is obtained by characterization and is not 100% tested.
µA ITCK = 0 to VLL,
TA = +25°C
(Note 1)
2015 Microchip Technology Inc.
DS20005412A-page 5
5 Page 
HV7351
1.1 Timing Diagrams
TCK = 1.65V (0.5VLL)
3.3V
TCK
0V
3.5 TCK cycles
3.3V
Internal CLK
(for N = 2)
0V
3.3V
tSU-TRIG
TRIG
0V
tWTRIG
+70V
tWTRIG needs to be at least
2 rising edges of TCK
TX1 0V
Delay time set by
TX1 10-bit counter
tdr1 tdf2
90%
90%
10%
tr1
10%
tf2
tdf1
10%
tdr2
10%
-70V
+70V
90%
tf1
90%
tr2
TX2 0V
-70V
FIGURE 1-1:
Delay time set by
TX2 10-bit counter
Example with TX2 delay having
two TCK cycles more than TX1
Timing Diagram of 3-Level, 1-Cycle Bipolar RTZ TX Pulse.
TCK = 1.65V (0.5VLL)
3.3V
TCK
0V
3.5 TCK cycles
3.3V
Internal CLK
(for N = 2) 0V
3.3V
TRIG
0V
+70V
tSU-TRIG
tWTRIG
tWTRIG needs to be at least
2 rising edges of TCK
TX1 0V
Delay time set by
TX1 10-bit counter
tdf3 tdr3
90%
90%
-70V
+70V
10%
tf3
10%
tr3
TX2 0V
-70V
FIGURE 1-2:
Delay time set by
TX2 10-bit counter
Example with TX2 delay having
one TCK cycle more than TX1
Timing Diagram of 2-Level 2-Cycle Bipolar, non-RTZ TX Pulses with Damping.
2015 Microchip Technology Inc.
DS20005412A-page 11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet HV7351.PDF ] | |
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