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AD9656 の電気的特性と機能

AD9656のメーカーはAnalog Devicesです、この部品の機能は「1.8 V Analog-to-Digital Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号
AD9656
部品説明
1.8 V Analog-to-Digital Converter
メーカ
Analog Devices
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Analog Devices ロゴ 




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AD9656 Datasheet, AD9656 PDF,ピン配置, 機能
Data Sheet
Quad, 16-Bit, 125 MSPS, JESD204B
1.8 V Analog-to-Digital Converter
AD9656
FEATURES
SNR = 79.9 dBFS at 16 MHz (VREF = 1.4 V)
SNR = 78.1 dBFS at 64 MHz (VREF = 1.4 V)
SFDR = 86 dBc to Nyquist (VREF = 1.4 V)
JESD204B Subclass 1 coded serial digital outputs
Flexible analog input range: 2.0 V p-p to 2.8 V p-p
1.8 V supply operation
Low power: 197 mW per channel at 125 MSPS (two lanes)
DNL = ±0.6 LSB (VREF = 1.4 V)
INL = ±4.5 LSB (VREF = 1.4 V)
650 MHz analog input bandwidth, full power
Serial port control
Full chip and individual channel power-down modes
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Standby mode
APPLICATIONS
Medical imaging
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Portable test equipment
GENERAL DESCRIPTION
The AD9656 is a quad, 16-bit, 125 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The device operates at a conversion rate of up to 125 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
Individual channel power-down is supported and typically
consumes less than 14 mW when all channels are disabled. The
ADC contains several features designed to maximize flexibility
and minimize system cost, such as a programmable output
clock, data alignment, and digital test pattern generation. The
available digital test patterns include built-in deterministic and
pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN DVDD DRVDD
VINA+
VINA–
VINB+
VINB–
RBIAS
VREF
SENSE
AGND
VINC+
VINC–
VIND+
VIND–
16
PIPELINE
ADC
16
PIPELINE
ADC
JESD204B
INTERFACE
REF
SELECT
1V
TO
1.4V
HIGH
SPEED
SERIALIZERS
16
PIPELINE
ADC
16
PIPELINE
ADC
CONTROL
REGISTERS
CML TX
OUTPUTS
VCM
SERIAL PORT
INTERFACE
CLOCK
MANAGEMENT
AD9656
SERDOUT0+
SERDOUT0–
SERDOUT1+
SERDOUT1–
SERDOUT2+
SERDOUT2–
SERDOUT3+
SERDOUT3–
DSYNC+
DSYNC–
Figure 1.
The AD9656 is available in an RoHS-compliant, nonmagnetic,
56-lead LFCSP.
It is specified over the −40°C to +85°C industrial temperature
range. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. It has a small footprint. Four ADCs are contained in a small, 8
mm × 8 mm package.
2. An on-chip phase-locked loop (PLL) allows users to provide
a single ADC sampling clock; the PLL multiplies the ADC
sampling clock to produce the corresponding JESD204B
data rate clock.
3. The configurable JESD204B output block supports up to
6.4 Gbps per lane.
4. JESD204B output block supports one, two, and four lane
configurations.
5. Low power of 198 mW per channel at 125 MSPS, two lanes.
6. The SPI control offers a wide range of flexible features to
meet specific system requirements.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.Datasheet4U.com

1 Page





AD9656 pdf, ピン配列
Data Sheet
AD9656
SPECIFICATIONS
DC SPECIFICATIONS, VREF = 1.4 V
AVDD = 1.8 V, DRVDD = 1.8 V, 2.8 V p-p full-scale differential input, 1.4 V reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 1.
Parameter1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Gain Error
Offset Error
INTERNAL VOLTAGE REFERENCE
Output Voltage
Load Regulation at 1.0 mA
Input Resistance
INPUT-REFERRED NOISE
VREF = 1.4 V
ANALOG INPUTS
Differential Input Voltage
Common-Mode Voltage
Common-Mode Range
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
AVDD
DVDD, DRVDD
IAVDD (125 MSPS, Two Lanes)2
IDVDD (125 MSPS, Two Lanes)2
IDRVDD (125 MSPS, Two Lanes)2
TOTAL POWER CONSUMPTION
DC Input (125 MSPS, Four Channels onto Two Lanes)
Sine Wave Input (125 MSPS, Four Channels onto Two Lanes)2
Power-Down Mode
Standby Mode3
Temperature
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Min Typ
16
−0.1
0
−1.0
0
−0.95
−10.0
Guaranteed
+0.14
0.1
+1.0
1.1
±0.6
±4.5
6.1
−2
1.37 1.4
4
7.5
2.1
2.8
0.9
0.7
2.6
7
1.7 1.8
1.7 1.8
288
67
83
706
788
14
547
Max Unit
Bits
+0.5
0.4
+3.1
2.0
+2.54
+10.0
% FSR
% FSR
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
1.41 V
mV
LSB rms
V p-p
V
1.1 V
pF
1.9 V
1.9 V
306 mA
72 mA
88 mA
mW
839 mW
mW
mW
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Measured with a low input frequency, full-scale sine wave on all four channels.
3 Standby can be controlled via the SPI.
Rev. 0 | Page 3 of 44
Free Datasheet http://www.Datasheet4U.com


3Pages


AD9656 電子部品, 半導体
AD9656
Data Sheet
Parameter1
CROSSTALK2
CROSSTALK (OVERRANGE CONDITION)3
ANALOG INPUT BANDWIDTH, FULL POWER
Temperature
25°C
25°C
25°C
Min Typ Max Unit
−93 dB
−89 dB
650 MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel.
3 Overrange condition is defined as the input being 3 dB above full scale.
AC SPECIFICATIONS, VREF = 1.0 V
AVDD = 1.8 V, DRVDD = 1.8 V, 2.0 V p-p full-scale differential input, 1.0 V reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 16 MHz
fIN = 64 MHz
fIN = 128 MHz
fIN = 201 MHz
fIN = 301 MHz
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) RATIO
fIN = 9.7 MHz
fIN = 16 MHz
fIN = 64 MHz
fIN = 128 MHz
fIN = 201 MHz
fIN = 301 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 16 MHz
fIN = 64 MHz
fIN = 128 MHz
fIN = 201 MHz
fIN = 301 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 16 MHz
fIN = 64 MHz
fIN = 128 MHz
fIN = 201 MHz
fIN = 301 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 16 MHz
fIN = 64 MHz
fIN = 128 MHz
fIN = 201 MHz
fIN = 301 MHz
WORST OTHER HARMONIC (EXCLUDING SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 16 MHz
fIN = 64 MHz
fIN = 128 MHz
fIN = 201 MHz
fIN = 301 MHz
Rev. 0 | Page 6 of 44
Temperature Min Typ Max
25°C 78
25°C 77.9
25°C 76.8
25°C 74.3
25°C 72.1
25°C 69.3
25°C 78
25°C 77.7
25°C 76.1
25°C 74
25°C 71.1
25°C 68.6
25°C 12.7
25°C 12.6
25°C 12.3
25°C 12.0
25°C 11.5
25°C 11.1
25°C 99
25°C 92
25°C 89
25°C 87
25°C 78
25°C 78
25°C −99
25°C −92
25°C −89
25°C −87
25°C −78
25°C −78
25°C −95
25°C −95
25°C −94
25°C −89
25°C −91
25°C −89
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
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合計 : 30 ページ
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