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ST62T20 の電気的特性と機能

ST62T20のメーカーはST Microelectronicsです、この部品の機能は「8-BIT OTP/EPROM MCUs」です。


製品の詳細 ( Datasheet PDF )

部品番号
ST62T20
部品説明
8-BIT OTP/EPROM MCUs
メーカ
ST Microelectronics
ロゴ

ST Microelectronics ロゴ 




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ST62T20 Datasheet, ST62T20 PDF,ピン配置, 機能
ST62T10, T15, T20, T25
- ST62E20, E25
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
s -40 to +85°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in OTP/EPROM
s Data OTP/EPROM: User selectable size
(in program EPROM)
s Data RAM: 64 bytes
s 12/20 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
s 4 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
s 8-bit Timer with 7-bit programmable prescaler
and external input
s Digital Watchdog
s 8-bit A/D Converter with 8 (ST62T10, T20, E20)
or 16 (ST62T15, T25, E25) analog inputs
s On-chip Clock oscillator can be driven by Quartz
crystal or Ceramic resonator
s Power-on Reset
s One external Non-Maskable Interrupt
s ST626x-EMU Emulation and Development
System (connects to an MS-DOS PC via an
RS232 serial line).
DEVICE SUMMARY
DEVICE
ST62T10
ST62T20
ST62E20
ST62T15
ST62T25
ST62E25
EPROM
(Bytes)
3884
3884
OTP
(Bytes)
1836
3884
I/O Pins
12
1836
3884
20
OTP PACKAGES
PDIP20
PDIP28
PSO20
PSO28
EPROM PACKAGES
CDIP20W
CDIP28W
(See end of Datasheet for Ordering Information)
July 1996
1/68
261

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ST62T20 pdf, ピン配列
Table of Contents
ST6210B, 15B, 20B, 25B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.3 Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.4 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.1 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.2 Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4.4 External Interrupt Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4.5 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3/68
263


3Pages


ST62T20 電子部品, 半導体
ST62T10, T15, T20, T25 - ST62E20, E25
1.2 PIN DESCRIPTION
VDD and VSS. Power is supplied to the MCU via
these two pins. VDD is the power connection and
VSS is the ground connection.
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is
the output pin.
RESET. The active-low RESET pin is used to re-
start the microcontroller.
TEST/VPP. The TEST must be held at VSS for nor-
mal operation. If TEST pin is connected to a
+12.5V level during the reset phase, the EPROM
programming Mode is entered.
NMI. The NMI pin provides the capability for asyn-
chronous interruption, by applying an external non
maskable interrupt to the MCU. The NMI input is
falling edge sensitive. A pull-up device must be
provided externally on OTP and EPROM devices.
TIMER. This is the timer I/O pin. In input mode it is
connected to the prescaler and acts as external
timer clock input or as control gate input for the in-
ternal timer clock. In output mode the timer pin
outputs the data bit when a time-out occurs. A
pull-up device must be provided externally on
OTP and EPROM devices.
Figure 2. ST62T10, T20, E20 Pin Configuration
PA0-PA3,PA4-PA7. These 8 lines are organized
as one I/O port (A). Each line may be configured
under software control as inputs with or without in-
ternal pull-up resistors, interrupt generating inputs
with pull-up resistors, open-drain or push-pull out-
puts. PA0-PA3 can also sink 20mA for direct LED
driving while PA4-PA7 can be programmed as an-
alog inputs for the A/D converter.
Note: PA4-PA7 are not available on ST62T10,
T20 or E20.
PB0-PB7. These 8 lines are organized as one I/O
port (B). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs, or as
analog inputs for the A/D converter.
PC4-PC7. These 4 lines are organized as one I/O
port (C). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs, or as
analog inputs for the A/D converter.
Note: PC4-PC7 are not available on ST62T10,
T20 or E20.
Figure 3. ST62T15, T25, E25 Pin Configuration
VDD
TIMER
OSCin
OSCout
NMI
VP P/TE ST
RESET
Ain/PB7
Ain/PB6
Ain/PB5
1
2
3
4
5
6
7
8
9
10
20 VSS
19 PA0
18 PA1
17 PA2
16 PA3
15 PB0/Ain
14 PB1/Ain
13 PB2/Ain
12 PB3/Ain
11 PB4/Ain
VDD
TIM ER
OSCin
OSCout
NMI
Ain/PC7
Ain/PC6
Ain/PC5
Ain/PC4
VPP/TES T
RESET
Ain/PB7
Ain/PB6
Ain/PB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VSS
27 PA0
26 PA1
25 PA2
24 PA3
23 PA4/Ain
22 PA5/Ain
21 PA6/Ain
20 PA7/Ain
19 PB0/Ain
18 PB1/Ain
17 PB2/Ain
16 PB3/Ain
15 PB4/Ain
6/68
266

6 Page

合計 : 30 ページ
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[ ST62T20 データシート.PDF ]

データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。

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部品番号部品説明メーカ
ST62T20

8-BIT OTP/EPROM MCUs

ST Microelectronics
ST Microelectronics
ST62T20C

(ST62T08C / ST62T09C / ST62T10C / ST62T20C / ST62E20C) 8-BIT OTP/EPROM MCUs

ST Microelectronics
ST Microelectronics
ST62T25

8-BIT OTP/EPROM MCUs

ST Microelectronics
ST Microelectronics
ST62T25

8-BIT OTP/EPROM MCUs

ST Microelectronics
ST Microelectronics

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