XCR3032 データシート PDFこの部品の機能は「32 Macrocell Cpld」です。 |
検索結果を表示する |
部品番号 |
XCR3032 32 Macrocell CPLD This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. www.Datasheet.jp 0 APPLICATION NOTE R XCR3032: 32 Macrocell CPLD 0 14* DS038 (v1.3) Octobe Xilinx |
文字列「 XCR3032 」「 3032 」で始まる検索結果です。 |
部品説明 |
XCR3032XL-10CS48C XCR3032XL 32 Macrocell CPLD 0 R XCR3032XL 32 Macrocell CPLD 0 14 DS023 (v1.5) January 8, 2002 Preliminary Product Specification Features • • • • • Lowest power 32 macrocell CPLD 5.0 ns pin-to-pin logic delays System frequencies up to 200 MHz 32 macrocells with 750 usable gates Available in sm Xilinx |
XCR3032XL-10CS48I XCR3032XL 32 Macrocell CPLD 0 R XCR3032XL 32 Macrocell CPLD 0 14 DS023 (v1.5) January 8, 2002 Preliminary Product Specification Features • • • • • Lowest power 32 macrocell CPLD 5.0 ns pin-to-pin logic delays System frequencies up to 200 MHz 32 macrocells with 750 usable gates Available in sm Xilinx |
XCR3032XL-10PC44C XCR3032XL 32 Macrocell CPLD 0 R XCR3032XL 32 Macrocell CPLD 0 14 DS023 (v1.5) January 8, 2002 Preliminary Product Specification Features • • • • • Lowest power 32 macrocell CPLD 5.0 ns pin-to-pin logic delays System frequencies up to 200 MHz 32 macrocells with 750 usable gates Available in sm Xilinx |
XCR3032XL-10PC44I XCR3032XL 32 Macrocell CPLD 0 R XCR3032XL 32 Macrocell CPLD 0 14 DS023 (v1.5) January 8, 2002 Preliminary Product Specification Features • • • • • Lowest power 32 macrocell CPLD 5.0 ns pin-to-pin logic delays System frequencies up to 200 MHz 32 macrocells with 750 usable gates Available in sm Xilinx |
XCR3032XL-10VQ44C XCR3032XL 32 Macrocell CPLD 0 R XCR3032XL 32 Macrocell CPLD 0 14 DS023 (v1.5) January 8, 2002 Preliminary Product Specification Features • • • • • Lowest power 32 macrocell CPLD 5.0 ns pin-to-pin logic delays System frequencies up to 200 MHz 32 macrocells with 750 usable gates Available in sm Xilinx |
XCR3032XL-10VQ44I XCR3032XL 32 Macrocell CPLD 0 R XCR3032XL 32 Macrocell CPLD 0 14 DS023 (v1.5) January 8, 2002 Preliminary Product Specification Features • • • • • Lowest power 32 macrocell CPLD 5.0 ns pin-to-pin logic delays System frequencies up to 200 MHz 32 macrocells with 750 usable gates Available in sm Xilinx |
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