XC9572-7PC44I データシート PDFこの部品の機能は「Xc9572 In-system Programmable Cpld」です。 |
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部品番号 |
XC9572-7PC44I XC9572 In-System Programmable CPLD 1 ® XC9572 In-System Programmable CPLD 1 1* December 4, 1998 (Version 3.0) Product Specification Features • • • • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 72 macroc Xilinx |
文字列「 XC95727PC44 」「 9572 」で始まる検索結果です。 |
部品説明 |
5962R9572701TEC Radiation Hardened Inverting 3-to-8 Line Decoder/Demultiplexer HCS138T Data Sheet July 1999 File Number 4614.1 Radiation Hardened Inverting 3-to-8 Line Decoder/Demultiplexer Intersil‘s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard � Intersil Corporation |
5962R9572701TXC Radiation Hardened Inverting 3-to-8 Line Decoder/Demultiplexer HCS138T Data Sheet July 1999 File Number 4614.1 Radiation Hardened Inverting 3-to-8 Line Decoder/Demultiplexer Intersil‘s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard � Intersil Corporation |
AD9572 Fiber Channel/Ethernet Clock Generator IC Fiber Channel/Ethernet Clock Generator IC, 7 Clock Outputs AD9572 FEATURES Fully integrated dual VCO/PLL cores 0.22 ps rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz 0.19 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz 0.42 ps rms jitter from 12 kHz to 20 MHz at 125 MHz Analog Devices |
XC9572 XC9572 In-System Programmable CPLD 1 ® XC9572 In-System Programmable CPLD 1 1* December 4, 1998 (Version 3.0) Product Specification Features • • • • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5 V in-system programmable ( Xilinx |
XC9572 XC9572XL High Performance CPLD 1 ® XC9572 In-System Programmable CPLD 1 1* December 4, 1998 (Version 3.0) Product Specification Features • • • • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5 V in-system programmable ( Xilinx |
XC9572-10PC44 XC9572 In-System Programmable CPLD 1 ® XC9572 In-System Programmable CPLD 1 1* December 4, 1998 (Version 3.0) Product Specification Features • • • • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5 V in-system programmable ( Xilinx |
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