XC9536XL データシート PDFこの部品の機能は「High Performance Cpld」です。 |
検索結果を表示する |
部品番号 |
XC9536XL High Performance CPLD 0 R XC9536XL High Performance CPLD DS058 (v1.9) April 3, 2007 00 Features • 5 ns pin-to-pin logic delays • System frequency up to 178 MHz • 36 macrocells with 800 usable gates • Available i Xilinx |
文字列「 XC9536 」「 9536XL 」で始まる検索結果です。 |
部品説明 |
XC9536 XC9536 In-System Programmable CPLD 9 1 ® XC9536 In-System Programmable CPLD 1 1* December 4, 1998 (Version 5.0) Product Specification Features • • • • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (I Xilinx |
XC9536-10 XC9536 In-System Programmable CPLD 9 1 ® XC9536 In-System Programmable CPLD 1 1* December 4, 1998 (Version 5.0) Product Specification Features • • • • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (I Xilinx |
XC9536-10CS48C XC9536 In-System Programmable CPLD 9 1 ® XC9536 In-System Programmable CPLD 1 1* December 4, 1998 (Version 5.0) Product Specification Features • • • • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (I Xilinx |
XC9536-10CS48I XC9536 In-System Programmable CPLD 9 1 ® XC9536 In-System Programmable CPLD 1 1* December 4, 1998 (Version 5.0) Product Specification Features • • • • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (I Xilinx |
XC9536-10PC44C XC9536 In-System Programmable CPLD 9 1 ® XC9536 In-System Programmable CPLD 1 1* December 4, 1998 (Version 5.0) Product Specification Features • • • • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (I Xilinx |
XC9536-10PC44I XC9536 In-System Programmable CPLD 9 1 ® XC9536 In-System Programmable CPLD 1 1* December 4, 1998 (Version 5.0) Product Specification Features • • • • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (I Xilinx |
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