XC95288XV-10 データシート PDFこの部品の機能は「High-performance Cpld」です。 |
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部品番号 |
XC95288XV-10 High-Performance CPLD 0 R XC95288XV High-Performance CPLD 0 5 DS050 (v2.2) August 27, 2001 Advance Product Specification Features • • 288 macrocells with 6,400 usable gates Available in small footprint packages - Xilinx |
文字列「 XC95288XV10 」「 95288XV 」で始まる検索結果です。 |
部品説明 |
XC95288 XC95288 In-System Programmable CPLD 0 ® XC95288 In-System Programmable CPLD 0 5* September 15, 1999 (Version 4.0) Product Specification Features • • • • • 10 ns pin-to-pin logic delays on all pins fCNT to 95 MHz 288 macrocells with 6,400 usable gates Up to 192 user I/O pins 5 V in-system programmabl Xilinx |
XC95288 XC95288XL High Performance CPLD 0 ® XC95288 In-System Programmable CPLD 0 5* September 15, 1999 (Version 4.0) Product Specification Features • • • • • 10 ns pin-to-pin logic delays on all pins fCNT to 95 MHz 288 macrocells with 6,400 usable gates Up to 192 user I/O pins 5 V in-system programmabl Xilinx |
XC95288-20HQ208C XC95288XL High Performance CPLD 0 R XC95288XL High Performance CPLD 0 5 DS055 (v1.5) June 20, 2002 Product Specification propagation delays of 6 ns. See Figure 2 for architecture overview. Features • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable Xilinx |
XC95288XL High Performance CPLD 0 R XC95288XL High Performance CPLD DS055 (v2.1 April 3, 2007 05 Features • 6 ns pin-to-pin logic delays • System frequency up to 208 MHz • 288 macrocells with 6,400 usable gates • Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP Xilinx |
XC95288XV High-Performance CPLD 0 R XC95288XV High-Performance CPLD 0 5 DS050 (v2.2) August 27, 2001 Advance Product Specification Features • • 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 280-pin CS Xilinx |
XC95288XV-5 High-Performance CPLD 0 R XC95288XV High-Performance CPLD 0 5 DS050 (v2.2) August 27, 2001 Advance Product Specification Features • • 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 280-pin CS Xilinx |
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