XC95216 データシート PDFこの部品の機能は「Xc95216 In-system Programmable Cpld」です。 |
検索結果を表示する |
部品番号 |
XC95216 XC95216 In-System Programmable CPLD 1 XC95216 In-System Programmable CPLD 1 0* August 21, 2001 (Version 3.1) Product Specification Features • • • • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 216 macro Xilinx |
文字列「 XC95216 」「 95216 」で始まる検索結果です。 |
部品説明 |
XC95216-10BG352C XC95216 In-System Programmable CPLD 1 XC95216 In-System Programmable CPLD 1 0* August 21, 2001 (Version 3.1) Product Specification Features • • • • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 216 macrocells with 4800 usable gates Up to 166 user I/O pins 5 V in-system programmable Xilinx |
XC95216-10BG352I XC95216 In-System Programmable CPLD 1 XC95216 In-System Programmable CPLD 1 0* August 21, 2001 (Version 3.1) Product Specification Features • • • • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 216 macrocells with 4800 usable gates Up to 166 user I/O pins 5 V in-system programmable Xilinx |
XC95216-10HQ208C XC95216 In-System Programmable CPLD 1 XC95216 In-System Programmable CPLD 1 0* August 21, 2001 (Version 3.1) Product Specification Features • • • • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 216 macrocells with 4800 usable gates Up to 166 user I/O pins 5 V in-system programmable Xilinx |
XC95216-10HQ208I XC95216 In-System Programmable CPLD 1 XC95216 In-System Programmable CPLD 1 0* August 21, 2001 (Version 3.1) Product Specification Features • • • • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 216 macrocells with 4800 usable gates Up to 166 user I/O pins 5 V in-system programmable Xilinx |
XC95216-10PQ160C XC95216 In-System Programmable CPLD 1 XC95216 In-System Programmable CPLD 1 0* August 21, 2001 (Version 3.1) Product Specification Features • • • • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 216 macrocells with 4800 usable gates Up to 166 user I/O pins 5 V in-system programmable Xilinx |
XC95216-10PQ160I XC95216 In-System Programmable CPLD 1 XC95216 In-System Programmable CPLD 1 0* August 21, 2001 (Version 3.1) Product Specification Features • • • • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 216 macrocells with 4800 usable gates Up to 166 user I/O pins 5 V in-system programmable Xilinx |
当社のサイトでは、半導体やセンサーからモーター、電源に至るまで、さまざまな製品のデータシートを簡単に検索してダウンロードできる集中型プラットフォームを提供しています。 |