XC95108-7PQ100I データシート PDFこの部品の機能は「Xc95108 In-system Programmable Cpld」です。 |
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部品番号 |
XC95108-7PQ100I XC95108 In-System Programmable CPLD 1 ® XC95108 In-System Programmable CPLD 1 1* December 4, 1998 (Version 3.0) Product Specification Features • • • • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 108 macr Xilinx |
文字列「 XC951087PQ100 」「 95108 」で始まる検索結果です。 |
部品説明 |
MB95108AM 8-bit Proprietary Microcontrollers FUJITSU SEMICONDUCTOR DATA SHEET DS07-12614-2E 8-bit Proprietary Microcontrollers CMOS F2MC-8FX MB95100AM Series MB95108AM/F104AMS/F104ANS/F104AJS/F106AMS/F106ANS/F106AJS/ MB95F108AMS/F108ANS/F108AJS/F104AMW/F104ANW/F104AJW/F106AMW/ MB95F106ANW/F106AJW/F10 Fujitsu Media Devices |
XC95108 XC95108 In-System Programmable CPLD 1 ® XC95108 In-System Programmable CPLD 1 1* December 4, 1998 (Version 3.0) Product Specification Features • • • • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 108 macrocells with 2400 usable gates Up to 108 user I/O pins 5 V in-system programmable Xilinx |
XC95108-10PC84C XC95108 In-System Programmable CPLD 1 ® XC95108 In-System Programmable CPLD 1 1* December 4, 1998 (Version 3.0) Product Specification Features • • • • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 108 macrocells with 2400 usable gates Up to 108 user I/O pins 5 V in-system programmable Xilinx |
XC95108-10PC84I XC95108 In-System Programmable CPLD 1 ® XC95108 In-System Programmable CPLD 1 1* December 4, 1998 (Version 3.0) Product Specification Features • • • • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 108 macrocells with 2400 usable gates Up to 108 user I/O pins 5 V in-system programmable Xilinx |
XC95108-10PQ100C XC95108 In-System Programmable CPLD 1 ® XC95108 In-System Programmable CPLD 1 1* December 4, 1998 (Version 3.0) Product Specification Features • • • • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 108 macrocells with 2400 usable gates Up to 108 user I/O pins 5 V in-system programmable Xilinx |
XC95108-10PQ100I XC95108 In-System Programmable CPLD 1 ® XC95108 In-System Programmable CPLD 1 1* December 4, 1998 (Version 3.0) Product Specification Features • • • • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 108 macrocells with 2400 usable gates Up to 108 user I/O pins 5 V in-system programmable Xilinx |
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