XC73144-7 データシート PDFこの部品の機能は「144-macrocell Cmos Epld」です。 |
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部品番号 |
XC73144-7 144-Macrocell CMOS EPLD ® XC73144 144-Macrocell CMOS EPLD Product Specifications Features • High-Performance EPLD – 7.5 ns pin-to-pin speed on all fast inputs – 100 MHz maximum clock frequency • Advanced Dual-Blo Xilinx |
文字列「 XC731447 」「 73144 」で始まる検索結果です。 |
部品説明 |
XC73144 XC7300 CMOS EPLD Family ® XC7300 CMOS EPLD Family Product Description Features • High-performance Erasable Programmable Logic Devices (EPLDs) – 5 / 7.5 ns pin-to-pin speeds on all fast inputs – Up to 167 MHz maximum clock frequency • Advanced Dual-Block architecture – Fast Function Blocks Xilinx |
XC73144 144-Macrocell CMOS EPLD ® XC7300 CMOS EPLD Family Product Description Features • High-performance Erasable Programmable Logic Devices (EPLDs) – 5 / 7.5 ns pin-to-pin speeds on all fast inputs – Up to 167 MHz maximum clock frequency • Advanced Dual-Block architecture – Fast Function Blocks Xilinx |
XC73144-10 144-Macrocell CMOS EPLD ® XC73144 144-Macrocell CMOS EPLD Product Specifications Features • High-Performance EPLD – 7.5 ns pin-to-pin speed on all fast inputs – 100 MHz maximum clock frequency • Advanced Dual-Block architecture – Four Fast Function Blocks – Twelve High-Density Function B Xilinx |
XC73144-12 144-Macrocell CMOS EPLD ® XC73144 144-Macrocell CMOS EPLD Product Specifications Features • High-Performance EPLD – 7.5 ns pin-to-pin speed on all fast inputs – 100 MHz maximum clock frequency • Advanced Dual-Block architecture – Four Fast Function Blocks – Twelve High-Density Function B Xilinx |
XC73144-15 144-Macrocell CMOS EPLD ® XC73144 144-Macrocell CMOS EPLD Product Specifications Features • High-Performance EPLD – 7.5 ns pin-to-pin speed on all fast inputs – 100 MHz maximum clock frequency • Advanced Dual-Block architecture – Four Fast Function Blocks – Twelve High-Density Function B Xilinx |
XC73144-7PQ160C 144-Macrocell CMOS EPLD ® XC73144 144-Macrocell CMOS EPLD Product Specifications Features • High-Performance EPLD – 7.5 ns pin-to-pin speed on all fast inputs – 100 MHz maximum clock frequency • Advanced Dual-Block architecture – Four Fast Function Blocks – Twelve High-Density Function B Xilinx |
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