VN0360N1 データシート PDFこの部品の機能は「N-channel Enhancement-mode VertICal Dmos Power Fets」です。 |
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部品番号 |
VN0360N1 N-Channel Enhancement-Mode Vertical DMOS Power FETs Supertex Inc |
文字列「 VN0360N1 」「 0360N1 」で始まる検索結果です。 |
部品説明 |
2506036017Y0 Chip Beads 15th Edition 27 Board Components Fair-Rite Products Corp. Phone: (888) FAIR RITE / (845) 895-2055 • FAX: (888) FERRITE / (845) 895-2629 (888) 324-7748 (888) 337 -7483 PO Box J, One Commercial Row, Wallkill, NY 12589-0288 • www.fair-rite.com • E-Mai Fair-Rite Products |
8403601JA 2K x 8 CMOS RAM HM-6516 March 1997 2K x 8 CMOS RAM Description The HM-6516 is a CMOS 2048 x 8 Static Random Access Memory. Extremely low power operation is achieved by the use of complementary MOS design techniques. This low power is further enhanced by the use of synchronous circuit techniques Intersil Corporation |
8403601ZA 2K x 8 CMOS RAM HM-6516 March 1997 2K x 8 CMOS RAM Description The HM-6516 is a CMOS 2048 x 8 Static Random Access Memory. Extremely low power operation is achieved by the use of complementary MOS design techniques. This low power is further enhanced by the use of synchronous circuit techniques Intersil Corporation |
AS8C403601 3.3V Synchronous SRAMS AS8C403601, AS8C401801,128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ Feature,3.3V I/O, burst counter, and Pipelined Outputs Commercial Temperature Ranges AS8C403601-QC166N AS8C401801-QC166N 403601/401801 403601/401801 403601/401801 NOVEMBER 1 AS8C403601, AS8C40180 Alliance Semiconductor |
AS8C403601-QC166N 3.3V Synchronous SRAMS AS8C403601, AS8C401801,128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ Feature,3.3V I/O, burst counter, and Pipelined Outputs Commercial Temperature Ranges AS8C403601-QC166N AS8C401801-QC166N 403601/401801 403601/401801 403601/401801 NOVEMBER 1 AS8C403601, AS8C40180 Alliance Semiconductor |
AS8C803601 3.3V Synchronous ZBT SRAMs 256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs ◆ AS8C803601 AS8C801801 Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or Alliance Semiconductor |
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