S-1334W-H データシート PDFこの部品の機能は「1300 Series Rectangular Connectors」です。 |
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部品番号 |
S-1334W-H 1300 SERIES RECTANGULAR CONNECTORS Hirose Electric |
文字列「 S1334 」「 S-13 」で始まる検索結果です。 |
部品説明 |
ADSP-21060KS-133 ADSP-2106x SHARC DSP Microcomputer Family a SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O 32-Bit IEEE Floating-Point Computation Units— Multiplier, ALU, and S Analog Devices |
ADSP-21060LKS-133 ADSP-2106x SHARC DSP Microcomputer Family a SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O 32-Bit IEEE Floating-Point Computation Units— Multiplier, ALU, and S Analog Devices |
ADSP-21061KS-133 ADSP-2106x SHARC DSP Microcomputer Family a SUMMARY High Performance Signal Computer for Speech, Sound, Graphics and Imaging Applications Super Harvard Architecture Computer (SHARC)— Four Independent Buses for Dual Data, Instructions, and I/O 32-Bit IEEE Floating-Point Computation Units— Multiplier, ALU and Shifter 1 Analog Devices |
ADSP-21062KS-133 ADSP-2106x SHARC DSP Microcomputer Family a SUMMARY High Performance Signal Processor for Communications, Graphics and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch and Nonintrusive I/O 32-Bit IEEE Floating-Point Computation Units— Multiplier, ALU, and Shi Analog Devices |
ADSP-21062LKS-133 ADSP-2106x SHARC DSP Microcomputer Family a SUMMARY High Performance Signal Processor for Communications, Graphics and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch and Nonintrusive I/O 32-Bit IEEE Floating-Point Computation Units— Multiplier, ALU, and Shi Analog Devices |
ADSP-2171BS-133 DSP Microcomputer a DSP Microcomputer ADSP-2171/ADSP-2172/ADSP-2173 FUNCTIONAL BLOCK DIAGRAM PROGRAM ROM 8K x 24 PROGRAM SEQUENCER PROGRAM RAM 2K x 24 MEMORY POWERDOWN CONTROL LOGIC FLAGS EXTERNAL ADDRESS BUS DATA ADDRESS GENERATORS DAG 1 DAG 2 FEATURES 30 ns Instruction Cycle Time (33 MIPS) fro Analog Devices |
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