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Datasheet PLL102-108 Equivalent ( PDF ) |
N.º | Número de pieza | Descripción | Fabricantes | |
1 | PLL102-108 | Programmable DDR Zero Delay Clock Driver PLL102-108
Programmable DDR Zero Delay Clock Driver
FEATURES
PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of ten differential outputs. • Track spread spectrum clocking for EMI reduction. • Programmable delay bet |
PhaseLink Corporation |
PLL102- Datasheet ( Hoja de datos ) - resultados coincidentes |
Número de pieza | Descripción | Fabricantes | |
PLL102-109 | Programmable DDR Zero Delay Clock Driver |
PhaseLink Corporation |
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PLL102-05 | Low Skew Output Buffer |
PhaseLink Corporation |
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PLL102-15 | Low Skew Output Buffer |
PhaseLink Corporation |
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Número de pieza | Descripción | Fabricantes | |
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Sanken |
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