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Datasheet PLL102-10 Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | |
| 3 | PLL102-10 | Low Skew Output Buffer PLL102-10
Low Skew Output Buffer
FEATURES
Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs. • Zero input - output delay. • Less than 700 ps device - device skew. • Less than 250 ps skew between outputs. www.Data |
 PhaseLink Corporation |
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| 2 | PLL102-108 | Programmable DDR Zero Delay Clock Driver PLL102-108
Programmable DDR Zero Delay Clock Driver
FEATURES
PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of ten differential outputs. • Track spread spectrum clocking for EMI reduction. • Programmable delay bet |
PhaseLink Corporation |
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| 1 | PLL102-109 | Programmable DDR Zero Delay Clock Driver Preliminary
PLL102-109
Programmable DDR Zero Delay Clock Driver
FEATURES
PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of six differential outputs. • Track spread spectrum clocking for EMI reduction. • Programm |
PhaseLink Corporation |
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