Datasheet IS61DDB22M18A Equivalent ( PDF )

N.º	Número de pieza	Descripción	Fabricantes	PDF
1	IS61DDB22M18A	36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM IS61DDB22M18A IS61DDB21M36A 2Mx18, 1Mx36 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM JANUARY 2015 FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip delay-locked loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed	Integrated Silicon Solution

IS61DDB22M Datasheet ( Hoja de datos ) - resultados coincidentes

Número de pieza	Descripción	Fabricantes	PDF
IS61DDB22M18	DDR-II (Burst of 2) CIO Synchronous SRAMs 36 Mb (1M x 36. & 2M x 18) ISSIDDR-II (Burst of 2) CIO Synchronous SRAMs ® Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late write operation. �	Integrated Silicon Solution
IS61DDB22M36A	72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM IS61DDB24M18A IS61DDB22M36A 4Mx18, 2Mx36 72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM AUGUST 2014 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip delay-locked loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline re	Integrated Silicon Solution
IS61DDB22M36	DDR-II (Burst of 2) CIO Synchronous SRAMs 72 Mb (2M x 36 & 4M x 18) . DDR-II (Burst of 2) CIO Synchronous SRAMs November 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late write operat	Integrated Silicon Solution

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