HY5S7B6LFP-H データシート PDFこの部品の機能は「512mbit Mobile Sdr Sdrams Based On 8m X 4bank X16i/o」です。 |
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部品番号 |
HY5S7B6LFP-H 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 0.4 1.0 Initial Draft Package size (10 x 13 [mm2]) D Hynix Semiconductor |
文字列「 HY5S7B6 」「 5S7B6LFP 」で始まる検索結果です。 |
部品説明 |
HY5S7B6ALFP-6 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 1.0 1.1 Initial Draft Inserted 166MHz Product Release Insert (Page10) DPD specification [IDD7 : 10uA min] History Draft Date Aug. 2006 S Hynix Semiconductor |
HY5S7B6ALFP-H 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 1.0 1.1 Initial Draft Inserted 166MHz Product Release Insert (Page10) DPD specification [IDD7 : 10uA min] History Draft Date Aug. 2006 S Hynix Semiconductor |
HY5S7B6ALFP-S 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 1.0 1.1 Initial Draft Inserted 166MHz Product Release Insert (Page10) DPD specification [IDD7 : 10uA min] History Draft Date Aug. 2006 S Hynix Semiconductor |
HY5S7B6LF-H 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 0.4 1.0 Initial Draft Package size (10 x 13 [mm2]) Defined DC Chatacteristics (Page 10 ~ 11) Modified Address # in Ball Description Hynix Semiconductor |
HY5S7B6LF-S 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 0.4 1.0 Initial Draft Package size (10 x 13 [mm2]) Defined DC Chatacteristics (Page 10 ~ 11) Modified Address # in Ball Description Hynix Semiconductor |
HY5S7B6LFP-S 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 0.4 1.0 Initial Draft Package size (10 x 13 [mm2]) Defined DC Chatacteristics (Page 10 ~ 11) Modified Address # in Ball Description Hynix Semiconductor |
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