DM74LS107A データシート PDFこの部品の機能は「Dual Negative-edge- Triggered Master-slave J-k Flip-flops」です。 |
検索結果を表示する |
部品番号 |
DM74LS107A Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops DM54LS107A DM74LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs June 1989 DM54LS107A DM74LS107A Dual Negative-EdgeTriggered Master-Slave J-K Flip- National Semiconductor |
文字列「 DM74LS107 」「 74LS107A 」で始まる検索結果です。 |
部品説明 |
74107 DUAL J-K FLIP FLOP WITH CLEAR M54HC107 M74HC107 DUAL J-K FLIP FLOP WITH CLEAR . HIGH SPEED fMAX = 75 MHz (TYP.) AT VCC = 5 V . LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C . HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) . OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS . SYMMETRICAL OUTPUT IMPEDANCE STMicroelectronics |
HD74LS107A Dual J-K Negative-edge-triggered Flip-Flops(with Clear) Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 Hitachi Semiconductor |
SN74107 Dual J-K Flip-Flops With Clear Texas Instruments |
SN74LS107A Dual J-K Flip-Flops With Clear Texas Instruments |
SN74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the other inputs and makes t Motorola Semiconductors |
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