enCoRe USB™ CY7C63722/23 CY7C63743 CY7C63722/23 CY7C63743 enCoRe™ USB Combination Low-Speed USB & PS/2 Peripheral Controller Cypress Semiconductor Corporation Document #: 38-08022 Rev. ** •

CY7C1471V33 CY7C1473V33 CY7C1475V33 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133 MHz bus operat

CY7C2168KV18/CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features ■ 18-Mbit density (1M × 18, 512K × 36) ■ 550-MHz clock for high bandwidt

CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM Features ■ True dual-ported memory cells that allow simultaneo

CY7C1223F 2-Mb (128K x 18) Pipelined DCD Sync SRAM Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 128K × 18-bit common I/O architecture • 3.

CY7C603xx enCoRe™ III Low Voltage enCoRe™ III Low Voltage Features ■ Powerful Harvard-architecture processor ❐ M8C processor speeds to 12 MHz ❐ Low power at high speed ❐ 2.4 V to 3.6 V operating voltage ❐ Operating voltages down to 1.0 V using on-chip switch mode p