enCoRe USB™ CY7C63722/23 CY7C63743 CY7C63722/23 CY7C63743 enCoRe™ USB Combination Low-Speed USB & PS/2 Peripheral Controller Cypress Semiconductor Corporation Document #: 38-08022 Rev. ** •

CY7C4425/4205/4215 CY7C4225/4235/4245 64/256/512/1K/2K/4K x 18 Synchronous FIFOs Features ■ High speed, low power, first-in first-out (FIFO) memories ■ 64 x 18 (CY7C4425) ■ 256 x 18 (CY7C4205) ■ 512 x 18 (CY7C4215) ■ 1K x 18 (CY7C4225) ■ 2K x 18 (CY7C4235) ■ 4K x 1

CY7C1461KV33 CY7C1463KV33 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture Features ■ No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles

CY7C65210, CY7C65217 USB Billboard Controller FcIESUSB Billboard Controller Features ■ USB 2.0-certified, Full-Speed (12 Mbps) ❐ Supports native Billboard Device class driver ❐ Integrated USB termination resistors ■ CY7C65210: Single channel I2C interface ❐ Master up t

CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 18-Mbit QDR™-II SRAM 2-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses ■ Doub

CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Configurations With Read Cycle Latency of 2.5 cycles: CY7C1161KV18 – 2 M x 8 CY7C1176KV18 – 2 M x 9 CY7C1163KV18 – 1 M x 18 CY7C