CY7C191 データシート PDFこの部品の機能は「(cy7c129 - Cy7c152) Ram9 Qdr-i/ddr-i/qdr-ii/ddr- Ii Errata」です。 |
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部品番号 |
CY7C191 (CY7C129 - CY7C152) RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata www.Datasheet.jp CY7C129*DV18/CY7C130*DV25 CY7C130*BV18/CY7C130*BV25/CY7C132*BV25 CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18 CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/ CY7C151*V18 /CY7C152*V18 Errata Cypress Semiconductor |
文字列「 CY7C191 」「 7C191 」で始まる検索結果です。 |
部品説明 |
CY7C1910BV18 1.8V Synchronous Pipelined SRAM CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 18-Mbit QDR™-II SRAM 2-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses ■ Doub Cypress Semiconductor |
CY7C1911BV18 (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth • 4-Word Burst for reducing address bus fr Cypress Semiconductor |
CY7C1911CV18 (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features ■ Configurations CY7C1311CV18 – 2M x 8 CY7C1911CV18 – 2M x 9 CY7C1313CV18 – 1M x 18 CY7C1315CV18 – 512K x 36 Separate independent read and write data ports Cypress Semiconductor |
CY7C1911JV18 (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR II SRAM 4-Word Burst Architecture Features ■ CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 ® Configurations CY7C1311JV18 – 2M x 8 CY7C1911JV18 – 2M x 9 CY7C1313JV18 – 1M x 18 CY7C1315JV18 – 512K x 36 Separate Independent Read and Write Data Ports Cypress Semiconductor |
CY7C1911KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture CY7C1311KV18/CY7C1911KV18 CY7C1313KV18/CY7C1315KV18 18-Mbit QDR® II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333-MHz clock for hi Cypress Semiconductor |
CY7C1916BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) Cypress Semiconductor |
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