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Datasheet CY7C166 Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | |
| 4 | CY7C166 | 16K x 4 Static RAM 66
CY7C164 CY7C166
16K x 4 Static RAM
Features
• High speed — 15 ns • Output enable (OE) feature (CY7C166) • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 110 mW • TTL-compatible inputs and outputs • Automatic power-down when deselected three-st |
 Cypress Semiconductor |
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| 3 | CY7C1663KV18 | 144-Mbit QDR II+ SRAM Four-Word Burst Architecture CY7C1663KV18/CY7C1665KV18
144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 550-MHz clock fo |
Cypress Semiconductor |
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| 2 | CY7C1665KV18 | 144-Mbit QDR II+ SRAM Four-Word Burst Architecture CY7C1663KV18/CY7C1665KV18
144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 550-MHz clock fo |
Cypress Semiconductor |
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| 1 | CY7C1668KV18 | 144-Mbit DDR II+ SRAM Two-Word Burst Architecture CY7C1668KV18 CY7C1670KV18
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
Features
■ 144-Mbit density (8 M × 18, 4 M × 36) ■ 550-MHz clock for high bandwidth ■ Two-word burst for reducing a |
Cypress Semiconductor |
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