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Datasheet CY7C152 Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | |
| 32 | CY7C152 | (CY7C129 - CY7C152) RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C129*DV18/CY7C130*DV25 CY7C130*BV18/CY7C130*BV25/CY7C132*BV25 CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18 CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/ CY7C151*V18 /CY7C152*V18 Errata Revision: *C
May 02, 2007 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
This document describes the DOFF |
 Cypress Semiconductor |
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| 31 | CY7C152*V18 | (CY7C129 - CY7C152) RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C129*DV18/CY7C130*DV25 CY7C130*BV18/CY7C130*BV25/CY7C132*BV25 CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18 CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/ CY7C151*V18 /CY7C152*V18 Errata Revision: *C
May 02, 2007 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
This document describes the DOFF |
Cypress Semiconductor |
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| 30 | CY7C1520KV18 | 72-Mbit DDR-II SRAM Two-Word Burst Architecture CY7C1518KV18 CY7C1520KV18
72-Mbit DDR-II SRAM Two-Word Burst Architecture
72-Mbit DDR-II SRAM Two-Word Burst Architecture
Features
■ 72-Mbit density (4M × 18, 2M × 36) ■ 333 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interface |
Cypress Semiconductor |
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| 29 | CY7C1520V18 | 1.8V Synchronous Pipelined SRAM CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18
72-Mbit DDR-II SRAM 2-Word Burst Architecture
Features
■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces
(data transf |
Cypress Semiconductor |
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| Número de pieza | Descripción | Fabricantes | |
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