CY7C147 データシート PDFこの部品の機能は「4k X 1 StatIC Ram」です。 |
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部品番号 |
CY7C147 4K x 1 STATIC RAM 7c147: 12/4/89 Revision: Thursday, November 11, 1993 www.Datasheet.jp Features D D D D D D D Automatic powerĆdown when deseĆ lected CMOS for optimum speed/power High speed Capable of withst Cypress Semiconductor |
文字列「 CY7C147 」「 7C147 」で始まる検索結果です。 |
部品説明 |
CY7C1470BV25 (CY7C147xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features ■ ■ Functional Description The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst SRAMs with N Cypress Semiconductor |
CY7C1470BV33 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features ■ Pin-compatible and functionally equivalent to ZBT™ ■ Suppor Cypress Semiconductor |
CY7C1470V25 (CY7C147xV25) 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM PRELIMINARY CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Availab Cypress Semiconductor |
CY7C1470V33 (CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed gra Cypress Semiconductor |
CY7C1471BV25 72-Mbit (2 M x 36) Flow-Through SRAM CY7C1471BV25 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture 72-Mbit (2 M × 36/1 M × 72) Flow-Through SRAM with NoBL™ Architecture Features ■ No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 13 Cypress Semiconductor |
CY7C1471BV33 72-Mbit (2 M x 36/4 M x 18) Flow-Through SRAM CY7C1471BV33 CY7C1473BV33 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture Features ■ No bus latency™ (NoBL™) architecture eliminates dead cycles between write and read cycle Cypress Semiconductor |
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