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Datasheet CY7C141 Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | |
| 33 | CY7C141 | 1K x 8 Dual-Port Static RAM CY7C130, CY7C130A CY7C131, CY7C131A
CY7C140, CY7C141
1K x 8 Dual-Port Static RAM
Features
■ True dual-ported memory cells, which allow simultaneous reads of the same memory location
■ 1K x 8 organization
■ 0.65 micron CMOS for optimum speed and power
■ High speed access: 15 ns
■ Low opera |
 Cypress Semiconductor |
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| 32 | CY7C1410AV18 | (CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18
36-Mbit QDR-II™ SRAM 2-Word Burst Architecture
Features
• Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth • 2-Word Burst on all accesses • Double Data Rate (DDR) inte |
Cypress Semiconductor |
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| 31 | CY7C1410JV18 | (CY7C14xxJV18) SRAM 2-Word Burst Architecture CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18
36-Mbit QDR™-II SRAM 2-Word Burst Architecture
Features
■
Configurations
CY7C1410JV18 – 4M x 8 CY7C1425JV18 – 4M x 9 CY7C1412JV18 – 2M x 18 CY7C1414JV18 – 1M x 36
Separate independent read and write data ports ❐ Supports concurre |
Cypress Semiconductor |
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| 30 | CY7C1410V18 | (CY7C14xxV18) SRAM 2-Word Burst Architecture PRELIMINARY
CY7C1410V18 CY7C1425V18 CY7C1412V18 CY7C1414V18
36-Mbit QDR-II™ SRAM 2-Word Burst Architecture
Features
• Separate Independent Read and Write data ports — Supports concurrent transactions • 200-MHz clock for high bandwidth • 2-Word Burst on all accesses • Double Data Rate ( |
Cypress Semiconductor |
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