Datasheet CY7C139 Equivalent ( PDF )

N.º	Número de pieza	Descripción	Fabricantes	PDF
10	CY7C139	4K x 8/9 Dual-Port Static RAM CY7C138 CY7C1394K x 8/9 Dual-Port Static RAM with Sem, Int, Busy CY7C138 CY7C139 Features • True Dual-Ported memory cells that allow simultaneous reads of the same memory location • 4K x 8 organization (CY7C138) • 4K x 9 organization (CY7C139) • 0.65-micron CMOS for optimum speed/power �	Cypress Semiconductor
9	CY7C1392BV18	1.8V Synchronous Pipelined SRAM CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces (d	Cypress Semiconductor
8	CY7C1392KV18	18-Mbit DDR II SIO SRAM Two-Word Burst Architecture CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features ■ 18-Mbit density (2M × 8, 1M × 18) ■ 333-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) in	Cypress Semiconductor
7	CY7C1393BV18	1.8V Synchronous Pipelined SRAM CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces (d	Cypress Semiconductor

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Número de pieza	Descripción	Fabricantes	PDF
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