CY7C1373C データシート PDFこの部品の機能は「18-mbit (512k X 36/1m X 18) Flow-through Sram With Nobl Architecture」です。 |
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部品番号 |
CY7C1373C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture CY7C1371C CY7C1373C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles Cypress |
文字列「 CY7C1373 」「 7C1373C 」で始まる検索結果です。 |
部品説明 |
CY7C1373B (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM 73B CY7C1371B CY7C1373B 512K x 36/1M x 18 Flow-Thru SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT devices • Supports 117-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-time Cypress Semiconductor |
CY7C1373D 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM CY7C1371D CY7C1373D 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features ■ No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles Cypress Semiconductor |
CY7C1373DV25 (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM CY7C1371DV25 CY7C1373DV25 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero Cypress Semiconductor |
CY7C1373KV33 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM CY7C1371KV33 CY7C1371KVE33 CY7C1373KV33 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC) 18-Mbit (512K × 36/1M × 18) Flow-through SRAM with NoBL™ Architecture (With ECC) Features ■ No Bus Latency (NoBL) architecture eliminates dead Cypress Semiconductor |
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