Datasheet CY7C1241V18 Equivalent ( PDF )

N.º	Número de pieza	Descripción	Fabricantes	PDF
1	CY7C1241V18	36-Mbit QDR-II SRAM 4-Word Burst Architecture CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features • Separate independent read and write data ports — Supports concurrent transactions • 300 MHz to 375 MHz clock for high bandwidth • 4-Word Burst for reducing a	Cypress Semiconductor

CY7C1241 Datasheet ( Hoja de datos ) - resultados coincidentes

Número de pieza	Descripción	Fabricantes	PDF
CY7C1241V18	36-Mbit QDR-II SRAM 4-Word Burst Architecture CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features • Separate independent read and write data ports — Supports concurrent transactions • 300 MHz to 375 MHz clock for high bandwidth • 4-Word	Cypress Semiconductor
CY7C1241KV18	36-Mbit QDR II SRAM 4-Word Burst Architecture 36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C1241KV18, CY7C1256KV18 CY7C1243KV18, CY7C1245KV18 ® Features ■ Configurations With Read Cycle Latency of 2.0 cycles: CY7C124	Cypress Semiconductor
CY7C12411KV18	36-Mbit QDR II SRAM 4-Word Burst Architecture 36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18 ® Features ■ Functional Description The CY7C12411KV18, CY7C12561KV18,	Cypress Semiconductor

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Número de pieza	Descripción	Fabricantes	PDF
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