CY7C107 PDF Datasheet

CY7C107 CY7C1007 1M x 1 Static RAM Features • High speed — tAA = 12 ns • CMOS for optimum speed/power • Low active power — 825 mW • Low standby power — 275 mW • 2.0V data retention (optional) — 100 µW • Automatic power-down when deselected • TTL-compatible inputs and outputs memory expansion is provided by an active LOW Chip Enable (

CY7C1071DV33 32-Mbit (2 M × 16) Static RAM 32-Mbit (2 M × 16) Static RAM Features ■ High speed ❐ tAA = 12 ns ■ Low active power ❐ ICC = 250 mA at 83.3 MHz ■ Low Complementary Metal Oxide Semiconductor (CMOS) standby power ❐ ISB2 = 50 mA ■ Operating voltages of 3.3 ± 0.3 V ■ 2.0 V data retention ■ Automatic power down when deselected ■ TTL compatible inpu

CY7C1079DV33 32-Mbit (4 M × 8) Static RAM 32-Mbit (4 M × 8) Static RAM Features ■ High Speed ❐ tAA = 12 ns ■ Low Active Power ❐ ICC = 250 mA at 12 ns ■ Low CMOS Standby Power ❐ ISB2 = 50 mA ■ Operating Voltages of 3.3 ± 0.3 V ■ 2.0 V Data Retention ■ Automatic Power Down when Deselected ■ TTL Compatible Inputs and Outputs ■ Available in Pb-free 48-ball

07B CY7C107B CY7C1007B 1M x 1 Static RAM Features • High speed — tAA = 12 ns • CMOS for optimum speed/power • Automatic power-down when deselected • TTL-compatible inputs and outputs Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the input pin (DIN) is written into the memory location specified on the addr

CY7C107D CY7C1007D 1-Mbit (1 M × 1) Static RAM 1-Mbit (1 M × 1) Static RAM Features ■ Pin- and function-compatible with CY7C107B/CY7C1007B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA @ 10 ns ■ Low complementary metal oxide semiconductor (CMOS) standby power ❐ ISB2 = 3 mA ■ 2.0 V data retention ■ Automatic power-down when deselected ■ CMOS