CLC402AMC データシート PDFこの部品の機能は「Low-gain Op Amp With Fast 14-bit Settling」です。 |
検索結果を表示する |
部品番号 |
CLC402AMC Low-Gain Op Amp with Fast 14-Bit Settling CLC402 Low-Gain Op Amp with Fast 14-Bit Settling June 1999 N CLC402 Low-Gain Op Amp with Fast 14-Bit Settling General Description Features s s s s s 0.0025% settling in 25ns (32ns max) 0.5mV input National Semiconductor |
文字列「 CLC402 」「 402AMC 」で始まる検索結果です。 |
部品説明 |
CLC402 Low-Gain Op Amp with Fast 14-Bit Settling CLC402 Low-Gain Op Amp with Fast 14-Bit Settling June 1999 N CLC402 Low-Gain Op Amp with Fast 14-Bit Settling General Description Features s s s s s 0.0025% settling in 25ns (32ns max) 0.5mV input offset voltage, 3µV/°C drift ±1 to ±8 closed-loop gain range Low power, 150m National Semiconductor |
CLC402 CLC402 Low-Gain Op Amp with Fast 14-bit Settling Texas Instruments |
CLC402A8B Low-Gain Op Amp with Fast 14-Bit Settling CLC402 Low-Gain Op Amp with Fast 14-Bit Settling June 1999 N CLC402 Low-Gain Op Amp with Fast 14-Bit Settling General Description Features s s s s s 0.0025% settling in 25ns (32ns max) 0.5mV input offset voltage, 3µV/°C drift ±1 to ±8 closed-loop gain range Low power, 150m National Semiconductor |
CLC402AJE Low-Gain Op Amp with Fast 14-Bit Settling CLC402 Low-Gain Op Amp with Fast 14-Bit Settling June 1999 N CLC402 Low-Gain Op Amp with Fast 14-Bit Settling General Description Features s s s s s 0.0025% settling in 25ns (32ns max) 0.5mV input offset voltage, 3µV/°C drift ±1 to ±8 closed-loop gain range Low power, 150m National Semiconductor |
CLC402AJP Low-Gain Op Amp with Fast 14-Bit Settling CLC402 Low-Gain Op Amp with Fast 14-Bit Settling June 1999 N CLC402 Low-Gain Op Amp with Fast 14-Bit Settling General Description Features s s s s s 0.0025% settling in 25ns (32ns max) 0.5mV input offset voltage, 3µV/°C drift ±1 to ±8 closed-loop gain range Low power, 150m National Semiconductor |
CLC402ALC Low-Gain Op Amp with Fast 14-Bit Settling CLC402 Low-Gain Op Amp with Fast 14-Bit Settling June 1999 N CLC402 Low-Gain Op Amp with Fast 14-Bit Settling General Description Features s s s s s 0.0025% settling in 25ns (32ns max) 0.5mV input offset voltage, 3µV/°C drift ±1 to ±8 closed-loop gain range Low power, 150m National Semiconductor |
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