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74HC73 データシート PDF 検索

番号 部品番号 部品説明 メーカ PDF
2 74HC73

Dual JK flip-flop

74HC73 Dual JK flip-flop with reset; negative-edge trigger Rev. 5 — 2 December 2015 Product data sheet 1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for

NXP
NXP
74HC73 データシート pdf
1 74HC73

Dual JK flip-flop with reset negative-edge trigger

74HC73 Dual JK flip-flop with reset; negative-edge trigger Rev. 03 — 12 November 2004 Product data sheet 1. General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. The 74HC is a dual negative-edge triggered JK flip-flop featuring indivi

Philips
Philips
74HC73 データシート pdf


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