Datasheet 74AUP1G373 Equivalent ( PDF )

N.º	Número de pieza	Descripción	Fabricantes	PDF
1	74AUP1G373	Low-power D-type transparent latch 3-state 74AUP1G373 Low-power D-type transparent latch; 3-state Rev. 03 — 9 January 2008 Product data sheet 1. General description The 74AUP1G373 provides the single D-type transparent latch with 3-state output. While the latch-enable (LE) input is high, the Q output follows the data	NXP Semiconductors

74AUP1G Datasheet ( Hoja de datos ) - resultados coincidentes

Número de pieza	Descripción	Fabricantes	PDF
74AUP1G04	Low power single inverter gate 74AUP1G04 Low power single inverter gate Features ■ ■ ■ ■ ■ ■ ■ High speed: tPD = 4.3 ns (max.) at VCC = 2.3 V Power down protection on inputs and outputs Balanced propagation delays: tPLH ≈ tPHL Operating voltage range: VCC (opr) = 1.2 to 3.	STMicroelectronics
74AUP1G11	Low-power 3-input AND gate 74AUP1G11 Low-power 3-input AND gate Rev. 01 — 4 September 2007 Product data sheet 1. General description The 74AUP1G11 provides a low-power, low-voltage single 3-input AND gate. Schmitt trigger action at all inputs makes the circuit tolerant to slower inp	NXP Semiconductors
74AUP1G07	SINGLE BUFFER/DRIVER 74AUP1G07 SINGLE BUFFER/DRIVER WITH OPEN DRAIN OUTPUT Description The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. Pin Assignments The 74AUP1G07 is a single buffer-gate, with an open drain outpu	Diodes

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Número de pieza	Descripción	Fabricantes	PDF
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