DataSheet.jp

CR16MPS544VI の電気的特性と機能

CR16MPS544VIのメーカーはNational Semiconductorです、この部品の機能は「Family of CompactRISC 16-Bit Microcontrollers」です。


製品の詳細 ( Datasheet PDF )

部品番号 CR16MPS544VI
部品説明 Family of CompactRISC 16-Bit Microcontrollers
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




このページの下部にプレビューとCR16MPS544VIダウンロード(pdfファイル)リンクがあります。
Total 70 pages

No Preview Available !

CR16MPS544VI Datasheet, CR16MPS544VI PDF,ピン配置, 機能
December 2001
CR16MES5/CR16MES9/CR16MFS5/CR16MFS9/
CR16MHS5/CR16MHS9/CR16MNS5/CR16MNS9/
CR16M9S5/CR16MUS5/CR16MUS9/
Family of CompactRISC 16-Bit Microcontrollers
1.0 General Description
The family of CompactRISC™ microcontrollers are gener-
al-purpose 16-bit microcontrollers based on a Reduced In-
struction Set Computer (RISC) architecture. The device
operates as a complete microcomputer with all system tim-
ing, interrupt logic, flash program memory or ROM memo-
ry, RAM, EEPROM data memory, and I/O ports included
on-chip. It is ideally suited to a wide range of embedded
controller applications because of its high performance,
on-chip integrated features and low power consumption,
resulting in decreased system cost.
The family of CompactRISC 16-bit microcontrollers offer
the high performance of a RISC architecture while retain-
ing the advantages of a traditional Complex Instruction Set
Computer (CISC): compact code, on-chip memory and I/O,
and reduced cost. The CPU uses a three-stage instruction
pipeline that allows execution of up to one instruction per
clock cycle, or up to 20 million instructions per second (MI-
PS) at a clock rate of 20 MHz.
Block Diagram
CR16B
Core
Processing
Unit
Core Bus
Fast Osc Slow Osc
Clock Generator
Power-on-Reset
Peripheral
Bus
Controller
48k Flash
Program
Memory
2 kbyte
RAM
640 Bytes
EEPROM
Data
Memory
boot
ROM
Interrupt
Control
(ICU)
Power-Save
Management
WATCHDOG
Peripheral Bus
I/O
µWire/SPI
Two
USARTs
Two
MFTs
A/D
MIWU
Two Analog
Comparators
Real-Time
Timer
Please note that not all family members contain same peripheral modules and features.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
©2001 National Semiconductor Corporation
www.national.com

1 Page





CR16MPS544VI pdf, ピン配列
1.0 General Description (Continued)
In the following text, device is alsays refered to the family of
CompactRISC 16-bit microcontrollers. For the exact feature
set, check individual datasheets.
The device is available in a variety of package sizes and
types. All devices have 48 kbytes of reprogrammable flash
program memory, 1.5 kbytes of ISP memory, 2 kbytes of stat-
ic RAM, and 640 bytes of non-volatile EEPROM data memo-
ry. The 80-pin device has two USARTs, two 16-bit multi-
function timers, one SPI/MICROWIRE-PLUS™ serial inter-
face, an 8-channel A/D converter, two analog comparators,
WATCHDOG™ protection mechanism, and up to 48 general-
purpose I/O pins. The 44-pin devices offer the same basic
features as the 80-pin device, but with fewer I/O ports and
peripheral modules due to the smaller number of available
pins.
All devices operate with a high-frequency crystal as the main
clock source. Some packages allow the device to operate
with either the main clock source or with a slow (32.768 KHz)
oscillator in Power Save mode. The device supports several
Power Save modes which are combined with multi-source in-
terrupt and wake-up capabilities.
Powerful cross-development tools are available from Nation-
al Semiconductor and third party suppliers to support the de-
velopment and debugging of application software for the
device. These tools let you program the application software
in C and are designed to take full advantage of the Compac-
tRISC architecture.
2.0 Features
CPU Features
— Fully static core, capable of operating at any rate from
0 to 20 MHz (4 MHz minimum in active mode)
— 50 ns instruction cycle time with a 20 MHz external
clock frequency
— Multi-source vectored interrupts (internal, external,
and on-chip peripheral)
— On-chip power-on reset
On-Chip Memory
— 48 kbytes of flash program memory or ROM memory
(100K cycle)
— 1.5 kbytes of ISP memory (100K cycle)
— 2 kbytes of static RAM data memory
— 640 bytes of non-volatile EEPROM data memory,
word-programmable (100K cycle)
On-Chip Peripherals
— Up to two Universal Synchronous/Asynchronous Re-
ceiver/Transmitter (USART) devices
— Programmable Idle Timer and real-time clock (T0)
— Up to two dual 16-bit multi-function timers (MFT1 and
MFT2)
— SPI/MICROWIRE-PLUS serial interface
— 8-channel, 8-bit Analog-to-Digital (A/D) converter with
external voltage reference, programmable sample-
and-hold delay, and programmable conversion fre-
quency
— Up to two analog comparators
— Integrated WATCHDOG logic
I/O Features
— Up to 48 general-purpose I/O pins (shared with on-chip
peripheral I/O pins)
— Programmable I/O pin characteristics: TRI-STATE out-
put, push-pull output, weak pull-up input, high-imped-
ance input
— Software-configurable Schmitt triggers on inputs
Power Supply
— 4.5V to 5.5V single-supply operation
Temperature Range
— 0°C to +70°C
— –40°C to +85°C
— –40°C to +125°C
Development Support
— Real-time emulation and full program debug capabili-
ties available
— CompactRISC tools provide C programming and de-
bugging support
3 www.national.com


3Pages


CR16MPS544VI 電子部品, 半導体
3.5 INTERRUPTS
The Interrupt Control Unit (ICU) receives interrupt requests
from internal and external sources and generates interrupts
to the CPU. An interrupt is an event that temporarily stops the
normal flow of program execution and causes a separate in-
terrupt service routine to be executed. After the interrupt is
serviced, CPU execution continues with the next instruction
in the program following the point of interruption.
Interrupts from the timers, USARTs, MICROWIRE/SPI inter-
face, multi-input wake-up, and A/D converter are all
maskable interrupts; they can be enabled or disabled by the
software. There are 16 of these maskable interrupts, orga-
nized into 16 predetermined levels of priority.
The highest-priority interrupt is the Non-Maskable Interrupt
(NMI), which is generated by a signal received on the NMI in-
put pin. This interrupt is not available in the 44-pin packages.
3.6 MULTI-INPUT WAKE-UP
The Multi-Input Wake-up (MIWU) module can be used for ei-
ther of two purposes: to provide inputs for waking up (exiting)
from the HALT, IDLE, or Power Save mode; or to provide
general-purpose edge-triggered maskable interrupts from
external sources. This eight-channel module generates one
combined interrupt to the CPU based on the signals received
on its eight input channels. Channels can be individually en-
abled or disabled, and programmed to respond to positive or
negative edges.
3.7 DUAL CLOCK AND RESET
The Dual Clock and Reset (CLK2RES) module generates a
high-speed main system clock from an external crystal net-
work. It also provides the main system reset signal and a
power-on reset function.
In the 80-pin package, the module also generates a slow sys-
tem clock (32.768 KHz) from another external crystal net-
work. The slow clock is used for operating the device in
power-save mode. For the 44-pin devices and for devices not
using a secondary crystal network, the slow clock can be
generated by dividing the high-speed main clock by a pres-
caler factor.
3.8 POWER MANAGEMENT
The Power Management Module (PMM) improves the effi-
ciency of the device by changing the operating mode (and
therefore the power consumption) according to the current
level of activity.
The device can operate in any of four power modes:
Active: The device operates at full speed using the high-
frequency clock. All device functions are fully operational.
Power Save: The device operates at reduced speed using
the slow clock. The CPU and some modules can continue
to operate at this low speed.
IDLE: The device is inactive except for the Power Man-
agement Module and Timing and Watchdog Module,
which continue to operate using the slow clock.
HALT: The device is inactive but still retains its internal
state (RAM and register contents).
3.9 MULTI-FUNCTION TIMER
The Multi-Function Timer (MFT16) module contains two inde-
pendent timer/counter units called MFT1 and MFT2, each
containing a pair of 16-bit timer/counter registers. Each timer/
counter unit can be configured to operate in any of the follow-
ing modes:
Processor-Independent Pulse Width Modulation (PWM)
mode, which generates pulses of a specified width and
duty cycle, and which also provides a general-purpose
timer/counter
Dual Input Capture mode, which measures the elapsed
time between occurrences of external events, and which
also provides a general-purpose timer/counter
Dual Independent Timer mode, which generates system
timing signals or counts occurrences of external events
Single Input Capture and Single Timer mode, which pro-
vides one external event counter and one system timer
3.10 REAL-TIME TIMER AND WATCHDOG
The Timing and Watchdog Module (TWM) generates the
clocks and interrupts used for timing periodic functions in the
system. It also provides Watchdog protection against soft-
ware errors. The module operates on the slow (32.768 KHz)
clock.
The real-time timer generates a periodic interrupt to the CPU
at a software-programmed interval. This can be used for real-
time functions such as a time-of-day clock.
The Watchdog is designed to detect program execution er-
rors such as an infinite loop or a “runaway” program. Once
Watchdog operation is initiated, the application program
must periodically write a specific value to a Watchdog regis-
ter, within specific time intervals. If the software fails to do so,
a Watchdog error is triggered, which resets the device.
3.11 USART
The USART is a Universal Synchronous/Asynchronous Re-
ceiver-Transmitter, a device used for serial communications.
It supports a wide range of programmable baud rates and
data formats, and handles parity generation and several er-
ror detection schemes. The baud rate is generated on-chip,
under software control.
The synchronous mode of operation is not available in the
44-pin devices.
3.12 MICROWIRE/SPI
The MICROWIRE/SPI (MWSPI) interface module supports
asynchronous serial communications with other devices that
conform to MICROWIRE or Serial Peripheral Interface (SPI)
specifications.
The MICROWIRE interface allows several devices to com-
municate over a single system consisting of three wires: se-
rial in, serial out, and shift clock. At any given time, one
device on the MICROWIRE interface operates as the master,
while all other devices operate as slaves. An 80-pin device
supports the full set of slave select and Ready lines for multi-
slave implementation, while a 44-pin device has only the ba-
sic Data-in/Data-out/Clock lines, limiting its implementation
to master mode.
www.national.com
6

6 Page



ページ 合計 : 70 ページ
 
PDF
ダウンロード
[ CR16MPS544VI データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
CR16MPS544VC

Family of CompactRISC 16-Bit Microcontrollers

National Semiconductor
National Semiconductor
CR16MPS544VI

Family of CompactRISC 16-Bit Microcontrollers

National Semiconductor
National Semiconductor


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap