CR16MNS544VC Datasheet PDF - National Semiconductor
| Part Number | CR16MNS544VC | |
| Description | Family of CompactRISC 16-Bit Microcontrollers | |
| Manufacturers | National Semiconductor | |
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December 2001
CR16MES5/CR16MES9/CR16MFS5/CR16MFS9/
CR16MHS5/CR16MHS9/CR16MNS5/CR16MNS9/
CR16M9S5/CR16MUS5/CR16MUS9/
Family of CompactRISC 16-Bit Microcontrollers
1.0 General Description
The family of CompactRISC™ microcontrollers are gener-
al-purpose 16-bit microcontrollers based on a Reduced In-
struction Set Computer (RISC) architecture. The device
operates as a complete microcomputer with all system tim-
ing, interrupt logic, flash program memory or ROM memo-
ry, RAM, EEPROM data memory, and I/O ports included
on-chip. It is ideally suited to a wide range of embedded
controller applications because of its high performance,
on-chip integrated features and low power consumption,
resulting in decreased system cost.
The family of CompactRISC 16-bit microcontrollers offer
the high performance of a RISC architecture while retain-
ing the advantages of a traditional Complex Instruction Set
Computer (CISC): compact code, on-chip memory and I/O,
and reduced cost. The CPU uses a three-stage instruction
pipeline that allows execution of up to one instruction per
clock cycle, or up to 20 million instructions per second (MI-
PS) at a clock rate of 20 MHz.
Block Diagram
CR16B
Core
Processing
Unit
Core Bus
Fast Osc Slow Osc
Clock Generator
Power-on-Reset
Peripheral
Bus
Controller
48k Flash
Program
Memory
2 kbyte
RAM
640 Bytes
EEPROM
Data
Memory
boot
ROM
Interrupt
Control
(ICU)
Power-Save
Management
WATCHDOG
Peripheral Bus
I/O
µWire/SPI
Two
USARTs
Two
MFTs
A/D
MIWU
Two Analog
Comparators
Real-Time
Timer
Please note that not all family members contain same peripheral modules and features.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
©2001 National Semiconductor Corporation
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3.0 Device Overview
The family of CompactRISC 16-bit microcontrollers are com-
plete microcomputers with all system timing, interrupt logic,
program memory, data memory, and I/O ports included on-
chip, making it well-suited to a wide range of embedded con-
troller applications.
3.1 CR16B CPU CORE
The device uses the CR16B CPU core module. This is the
same core used in other CompactRISC family members.
The high performance of the CPU core results from the im-
plementation of a pipelined architecture with a two-bytes-per-
cycle pipelined system bus. As a result, the CPU can support
a peak execution rate of one instruction per clock cycle.
Compared with conventional RISC processors, the device
differs in the following ways:
• The CPU core uses on-chip rather than external memory.
This eliminates the need for large and complex bus inter-
face units.
• Most instructions are 16 bits, so all basic instructions are
just two bytes long. (Additional bytes are sometimes re-
quired for immediate values, so instructions can be two or
four bytes long.)
• Non-aligned word access is allowed. Each instruction can
operate on 8-bit or 16-bit.
• The device is designed to operate with a clock rate in the
10 to 25 MHz range rather than 100 MHz or more. Most
embedded systems face EMI and noise constraints that
limit clock speed to these lower ranges. A lower clock
speed means a simpler, less costly silicon implementa-
tion.
• The instruction pipeline uses three stages. A smaller pipe-
line eliminates the need for costly branch prediction
mechanisms and bypass registers, while maintaining ad-
equate performance for typical embedded controller ap-
plications.
3.2 MEMORY
The CompactRISC architecture supports a uniform linear ad-
dress space of 2 megabytes. The device implementation of
this architecture uses only the lowest 64 kbytes of address
space. Four types of on-chip memory occupy specific inter-
vals within this address space: 48 kbytes of flash program
memory, 1.5 kbytes of ISP memory, 2 kbytes of static RAM,
and 640 bytes of EEPROM data memory.
The 48 kbytes of flash program memory are used to store the
application program. It has security features to prevent unin-
tentional programming and to prevent unauthorized access
to the program code. This memory can be programmed ei-
ther with the device plugged into an EPROM programmer
unit (external programming) or with the device installed in the
application system (in-system programming).
The 2 kbytes of static RAM are used for temporary storage of
data and for the program stack and interrupt stack. Read and
write operations can be byte-wide or word-wide, depending
on the instruction executed by the CPU. Each memory ac-
cess requires one clock cycle; no wait cycles or hold cycles
are required.
The 640 bytes of EEPROM data memory are used for non-
volatile storage of data, such as configuration settings en-
tered by the end-user. The CPU reads or writes this memory
by using ordinary byte-wide or word-wide memory access
commands. After the CPU performs a write to this memory,
the on-chip hardware completes the EEPROM programming
in the background. A register status bit indicates the status of
the EEPROM programming operation.
There is a factory programmed boot memory used to store
In-System-Programming (ISP) code. (this code allows pro-
gramming of the program memory via one of the USART in-
terfaces in the final application.)
For the flash program memory, the device internally gener-
ates the necessary voltages for programming. No additional
power supply is required.
3.3 INPUT/OUTPUT PORTS
Each device has 48 software-configurable I/O pins, orga-
nized into six 8-pin ports called Port B, Port C, Port F, Port G,
Port L, and Port I. Each pin can be configured to operate as
a general-purpose input or general-purpose output. In addi-
tion, many I/O pins can be configured to operate as a desig-
nated input or output for an on-chip peripheral module such
as the USART, timer, A/D converter, or MICROWIRE/SPI in-
terface.
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, push-
pull output, weak pull-up input, or high-impedance input. In-
put pins can be software-configured to use Schmitt triggers
for noise resistance.
Each 44-pin device has a subset of the pins available in the
80-pin device. This results in the loss of some features that
are available in the larger-package device:
• One of the two USARTs or one of the two multi-function
timers (depending on package selection)
• Synchronous mode in the remaining USART(s)
• Slave mode operation for the MICROWIRE/SPI interface
• Separate external VREF for the A/D converter
• Comparators
• Four of the eight Multi-Input Wakeup pins
• NMI interrupt input pin
3.4 BUS INTERFACE UNIT
The Bus Interface Unit (BIU) controls the interface between
the on-chip modules to the internal core bus. It determines
the configured parameters for bus access (such as the num-
ber of wait states for memory access) and issues the appro-
priate bus signals for each requested access.
The BIU uses a set of control registers to determine how
many wait states and hold states are to be used when ac-
cessing EEPROM memory. Upon start-up of the device,
these registers must be programmed with appropriate values
so that the minimum allowable number states is used. This
number varies with the clock frequency and the type of on-
chip device being accessed.
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Featured Datasheets
| Part Number | Description | MFRS |
| CR16MNS544VC | The function is Family of CompactRISC 16-Bit Microcontrollers. National Semiconductor | |
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