PDF IS45S32400B Data sheet ( Hoja de datos )

Número de pieza	IS45S32400B
Descripción	128-MBIT SYNCHRONOUS DRAM
Fabricantes	ISSI
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No Preview Available ! IS45S32400B 4Meg x 32 128-MBIT SYNCHRONOUS DRAM ISSI® JULY 2006 FEATURES • Clock frequency: 166, 143, 125, 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS45S32400B VDD VDDQ 3.3V 3.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Auto Refresh (CBR) • Self Refresh with programmable refresh periods • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Automotive Temperature Range Option A: 0oC to +70oC Option A1: -40oC to +85oC • Available in 86-pin TSOP-II and 90-ball FBGA • Available in Lead-free OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 -7 67 8 10 166 143 125 100 5.4 5.4 6.5 6.5 Unit ns ns Mhz Mhz ns ns Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/10/06 1 1 page IS45S32400B PIN FUNCTIONS Symbol A0-A11 Type Input Pin BA0, BA1 CAS CKE CLK CS DQM0-DQM3 Input Pin Input Pin Input Pin Input Pin Input Pin Input Pin DQ0-DQ31 RAS WE VDDQ VDD VSSQ VSS Input/Output Pin Input Pin Input Pin Power Supply Pin Power Supply Pin Power Supply Pin Power Supply Pin ISSI ® Function (In Detail) Address Inputs: A0-A11 are sampled during the ACTIVE command (row-address A0-A11) and READ/WRITE command (column address A0- A7), with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth Table" for details on device commands. The CKE input determines whether the CLK input is enabled. The next rising edge of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW, the device will be in either power-down mode, clock suspend mode, or self refresh mode. CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. DQM0 - DQM3 control the four bytes of the I/O buffers (DQ0-DQ31). In read mode, DQMn control the output buffer. When DQMn is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state whenDQMn is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, DQMn control the input buffer. When DQMn is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When DQMn is HIGH, input data is masked and cannot be written to the device. Data on the Data Bus is latched on these pins during Write commands, and buffered after Read commands. RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands. VDDQ is the output buffer power supply. VDD is the device internal power supply. VSSQ is the output buffer ground. VSS is the device internal ground. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/10/06 5 5 Page IS45S32400B ISSI ® FUNCTIONAL TRUTH TABLE Continued: Current State CS RAS CAS WE Address Command Action Write Recovering H × ×× × DESL Nop, Enter row active after tDPL LH H H × NOP Nop, Enter row active after tDPL LH H L LH L H × BA, CA, A10 BST Nop, Enter row active after tDPL READ/READA Begin read (8) LH L L LL HH LL HL BA, CA, A10 BA, RA BA, A10 WRIT/ WRITA ACT PRE/PALL Begin new write ILLEGAL (3) ILLEGAL (3) LL L H × REF/SELF ILLEGAL LL L L OC, BA MRS ILLEGAL Write Recovering H × × × × DESL Nop, Enter precharge after tDPL with Auto LH H H × NOP Nop, Enter precharge after tDPL Precharge LH H L LH L H LH L L LL HH LL HL × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 BST READ/READA WRIT/WRITA ACT PRE/PALL Nop, Enter row active after tDPL ILLEGAL(3,8,11) ILLEGAL (3,11) ILLEGAL (3,11) ILLEGAL (3,11) LL L H × REF/SELF ILLEGAL LL L L OC, BA MRS ILLEGAL Refresh H× × × × DESL Nop, Enter idle after tRC LH H × × NOP/BST Nop, Enter idle after tRC LH L H BA, CA, A10 READ/READA ILLEGAL LH L L BA, CA, A10 WRIT/WRITA ILLEGAL LL H H BA, RA ACT ILLEGAL LL HL BA, A10 PRE/PALL ILLEGAL LL L H × REF/SELF ILLEGAL LL L L OC, BA MRS ILLEGAL Mode Register H× ×× × DESL Nop, Enter idle after 2 clocks Accessing LH H H × NOP Nop, Enter idle after 2 clocks LH H L × BST ILLEGAL LH L × BA, CA, A10 READ/WRITE ILLEGAL LL × × BA, RA ACT/PRE/PALL ILLEGAL REF/MRS Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Notes: 1. All entries assume that CKE is active (CKEn-1=CKEn=H). 2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data which don’t satisfy tDPL. 10. Illegal if tRRD is not satisfied. 11. Illegal for single bank, but legal for other banks. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/10/06 11 11 Page

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